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Da ta Sh ee t, D S 1, D ec em be r 20 01
ABM 3G A T M B uf f e r M a na ge r
P XF 4 33 3 V e r s i on 1 . 1
W ir ed Co m mu n ic a ti o n s
Never stop thinking.
Edition 2001-12-17 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da ta Sh ee t, D S 1, D ec em be r 20 01
ABM 3G A T M B uf f e r M a na ge r
P XF 4 33 3 V e r s i on 1 . 1
W ir ed Co m mu n ic a ti o n s
Never stop thinking.
*
ABM-3G Data Sheet Revision History: Previous Version: Page 2001-12-17 none DS 1
Subjects (major changes since last revision) Reworked from preliminary to first finalized status
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
Disclaimer: This data sheet describes a product under development by Infineon Technologies AG (`Infineon'). Infineon reserves the right to change features and characteristics of the product or to discontinue this product without notice. None of the information contained in this document constitutes an express or implied assurance of availability or functionality. Please contact Infineon for the latest information on the product.
ABM-3G PXF 4333 V1.1
Table of Contents 1 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.2 1.3 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 3 3.1 3.1.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.5.1 3.2.5.2 3.2.5.3 3.2.5.4 3.2.6 3.3 Page 19 20 20 21 21 22 22 23 24 25 25 26 27 27 28 29 31 32 33 35 37 39 40 41 41 42 43 43 45 46 46 46 46 47 52 52 53 53 54 54 55
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queueing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scheduling Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram with Functional Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common System Clock Supply (3 pins) . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Receive Interface Upstream (Master/Slave) (32 pins) . . . . . . UTOPIA Transmit Interface Downstream (Master/Slave) (32 pins) . . . . UTOPIA Receive Interface Downstream (Master/Slave) (32 pins) . . . . UTOPIA Transmit Interface Upstream (Master/Slave) (32 pins) . . . . . . Microprocessor Interface (32 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Storage RAM Upstream (50 pins) . . . . . . . . . . . . . . . . . . . . . . . . . Cell Storage RAM Downstream (50 pins) . . . . . . . . . . . . . . . . . . . . . . . Common Up- and Downstream Cell Pointer RAM (42 pins) . . . . . . . . . JTAG Boundary Scan (5 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Production Test (2 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply (74 VSS, 32 VDD33 and 14 VDD18 pins) . . . . . . . . . . . . . . . . . Unconnected (13 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Throughput and Speedup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Handler (Upstream/Downstream) . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Manager and Queue Scheduler (Overview) . . . . . . . . . . . . . . . . AAL5 Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Address Reduction Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPLL Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Table of Contents 3.3.1 3.4 3.4.1 3.4.1.1 3.4.1.2 3.4.1.3 3.4.1.4 3.4.1.5 3.4.1.6 3.4.1.7 3.4.1.8 3.4.2 3.4.2.1 3.4.2.2 3.4.2.3 3.4.2.4 3.4.2.5 3.4.3 3.4.4 3.4.5 3.4.5.1 3.4.5.2 3.4.5.3 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.5.9.1 3.5.9.2 3.5.9.3 4 4.1 4.2 4.2.1 4.2.2 4.2.2.1 Page 58 60 61 61 62 64 65 65 67 71 74 76 76 77 79 81 86 88 89 90 90 90 90 93 93 94 94 94 94 94 94 95 95 95 97 99 100 100 100 105 106 106
LCI Translation in Mini-Switch Configurations . . . . . . . . . . . . . . . . . . . . Buffer Manager and Queue Scheduler Details . . . . . . . . . . . . . . . . . . . . . Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Buffer Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Threshold Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Threshold and Occupancy Counter Overview . . . . . . . . . . . . . . . . . . Discard Mechanisms and Buffer Reservation . . . . . . . . . . . . . . . . . . Cell Acceptance Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Statistical Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queue Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scheduler Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality of Service Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC-Merge and Dummy Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scheduler Block Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scheduler Block Scheduler (SBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Header Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Queue Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCI: Local Connection Identifier Table . . . . . . . . . . . . . . . . . . . . . . . . . . QCT: Queue Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QPT: Queue Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCT: Traffic Class Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SBOC: Scheduler Block Occupancy Table . . . . . . . . . . . . . . . . . . . . . . SCT: Scheduler Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . MGT: Merge Group Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVT: VBR Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVT Context RAM Organization and Addressing . . . . . . . . . . . . . . . AVT Context RAM Section for VBR Shaping Support . . . . . . . . . . . . Common AVT CONFIG Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Traffic Management Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . Setup of Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Queue Scheduler Rates and Granularities . . . . . . . . . . Scheduler Block Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Table of Contents 4.2.2.2 4.2.2.3 4.2.2.4 4.2.2.5 4.2.2.6 4.2.2.7 4.2.3 4.2.4 4.2.5 4.2.5.1 4.2.6 4.2.7 4.2.7.1 4.2.7.2 4.2.7.3 4.2.7.4 4.2.7.5 4.2.7.6 4.2.7.7 4.3 4.4 4.4.1 4.4.2 4.5 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.6.1 5.1.6.2 5.1.6.3 5.1.6.4 5.1.6.5 5.2 5.2.1 5.2.2 5.2.3 5.2.4 Page 106 109 109 109 112 114 115 116 116 117 118 119 119 119 119 119 120 120 120 121 121 121 121 123 124 124 124 125 127 128 129 130 130 131 131 132 132 134 134 134 134 134
Programming the Scheduler Block Rates . . . . . . . . . . . . . . . . . . . . Programming the Common Real-Time Bypass . . . . . . . . . . . . . . . . Programming the SDRAM Refresh Empty Cell Cycles . . . . . . . . . . Programming the PCR Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Leaky Bucket Shaper . . . . . . . . . . . . . . . . . . . . . Guaranteed Cell Rates and WFQ Weight Factors . . . . . . . . . . . . . . ABM-3G Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bandwidth Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bandwidth Reservation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support of Standard ATM Service Categories . . . . . . . . . . . . . . . . . . . CBR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rt-VBR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nrt-VBR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UBR+ Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GFR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UBR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Service Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Teardown Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAL5 Packet Insertion/Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAL5 Packet Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AAL5 Packet Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA L2 Interfaces (PHY side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . URXU: UTOPIA Receive Upstream (PHY side) . . . . . . . . . . . . . . . . . UTXD: UTOPIA Transmit Downstream (PHY side) . . . . . . . . . . . . . . . UTOPIA Port/Address Mapping (PHY side) . . . . . . . . . . . . . . . . . . . . Functional UTOPIA Timing (PHY side) . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Master Mode Polling Scheme (PHY side) . . . . . . . . . . . . . . . UTOPIA Cell Format (PHY side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTOPIA Level 2 Standard Cell Formats . . . . . . . . . . . . . . . . . . . . . LCI Mapping Mode: VPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCI Mapping Mode: VCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCI Mapping Mode: Infineon Mode . . . . . . . . . . . . . . . . . . . . . . . . . LCI Mapping Mode: Address Reduction Mode . . . . . . . . . . . . . . . . UTOPIA L2 Interface (Backplane side) . . . . . . . . . . . . . . . . . . . . . . . . . . URXD: UTOPIA Receive Downstream (Backplane side) . . . . . . . . . . UTXU: UTOPIA Transmit Upstream (Backplane side) . . . . . . . . . . . . UTOPIA Port/Address Mapping (Backplane side) . . . . . . . . . . . . . . . . Functional UTOPIA Timing (Backplane side) . . . . . . . . . . . . . . . . . . .
7
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Table of Contents 5.2.5 5.2.6 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.4 5.4.1 5.5 5.6 5.6.1 5.6.2 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 Page 134 135 135 135 136 136 137 137 138 138 141 141 141 141
UTOPIA Master Mode Polling Scheme (Backplane side) . . . . . . . . . . UTOPIA Cell Format (Backplane side) . . . . . . . . . . . . . . . . . . . . . . . . MPI: Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External RAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of the ABM-3G Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Flow Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Insertion/Extraction and AAL5 Control Registers . . . . . . . . . . . . . Buffer Occupation Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Threshold and Occupation Capture Registers . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Backpressure Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCI Table Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Class Table Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . Queue Configuration Table Transfer Registers . . . . . . . . . . . . . . . . . . Scheduler Block Occupancy Table Transfer Registers . . . . . . . . . . . . Merge Group Table Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rate Shaper CDV Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queue Parameter Table Mask Registers . . . . . . . . . . . . . . . . . . . . . . Scheduler Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queue Parameter Table Transfer Registers . . . . . . . . . . . . . . . . . . . . Scheduler Block Configuration Table Transfer/Mask Registers SDRAM Refresh Registers UTOPIA Port Select of Common Real Time Queue Registers 257 Scheduler Block Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Real Time Queue Rate Registers . . . . . . . . . . . . . . . . . . . . AVT Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
143 143 156 156 157 158 174 176 181 181 191 195 211 223 230 235 239 240 246 247
7.2.19 7.2.20 7.2.21
270 278 280
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Table of Contents 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 8 8.1 8.2 8.3 8.4 8.4.1 8.4.1.1 8.4.1.2 8.4.2 8.4.2.1 8.4.2.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.5 8.6 9 10 11 Page 287 290 295 297 307 311 317 335 336 336 336 337 339 340 340 341 342 342 343 345 350 351 353 354 355 355
PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External RAM Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABM-3G Version Code Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status/Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global ABM-3G Status and Mode Registers . . . . . . . . . . . . . . . . . . . . UTOPIA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Registers/Special Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface Timing Intel Mode . . . . . . . . . . . . . . . . . . . . Microprocessor Write Cycle Timing (Intel) . . . . . . . . . . . . . . . . . . . . Microprocessor Read Cycle Timing (Intel) . . . . . . . . . . . . . . . . . . . . Microprocessor Interface Timing Motorola Mode . . . . . . . . . . . . . . . . Microprocessor Write Cycle Timing (Motorola) . . . . . . . . . . . . . . . . Microprocessor Read Cycle Timing (Motorola) . . . . . . . . . . . . . . . . UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPR SSRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR SDRAM Interface(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
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List of Figures Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-18 Figure 3-19 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-25 Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-31 Figure 3-32 Figure 3-33 Figure 3-34 Figure 3-36 Figure 3-37 Figure 4-1 Figure 4-7 Figure 4-9 Figure 4-10 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4
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Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin Configuration (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Configuration (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Sub-System Integration Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Logical Block Diagram (One Direction) . . . . . . . . . . . . . . . . . . . . . . . . 45 LCI Building Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LCI Building Patterns (VPI only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Clocking System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DPLL Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Reset System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ABM-3G in Bi-directional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ABM-3G in Uni-directional Mode Using both Cores. . . . . . . . . . . . . . . 57 ABM-3G in Uni-directional Mode Using one Core . . . . . . . . . . . . . . . . 57 Connection Identifiers in Mini-Switch Configuration. . . . . . . . . . . . . . . 58 Cell Acceptance and Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Buffer Manager Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Queue Assignment to Traffic Classes and Scheduler Blocks . . . . . . . 63 Buffer Management with per Queue Minimum Buffer Reservation . . . 70 Buffer Threshold with Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Functional Structure of the Hierarchical Queue Scheduler . . . . . . . . . 76 Scheduler Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Behavior of Different Scheduler Types . . . . . . . . . . . . . . . . . . . . . . . . 78 Scheduler Behavior Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Shaping and Policing at Network Boundaries . . . . . . . . . . . . . . . . . . . 81 Ideal ABM-3G Shaper Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Ideal and Real ABM-3G Shaper Output. . . . . . . . . . . . . . . . . . . . . . . . 83 VC Merge Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Scheduler Block Usage at Switch Output . . . . . . . . . . . . . . . . . . . . . . 88 Scheduler Block Usage at Switch Input . . . . . . . . . . . . . . . . . . . . . . . . 89 SCAN Timer Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 AVT Context RAM Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . 96 Parameters for Connection Setup (bit field width indicated) . . . . . . . 101 ABM-3G Application Example: DSLAM . . . . . . . . . . . . . . . . . . . . . . . 115 Example of Threshold Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 118 AAL5 Extraction: End of packet, Trailer and Status Byte. . . . . . . . . . 122 UTOPIA Receive Upstream Master Mode . . . . . . . . . . . . . . . . . . . . . 124 UTOPIA Receive Upstream Slave Mode . . . . . . . . . . . . . . . . . . . . . . 124 UTOPIA Transmit Downstream Master Mode . . . . . . . . . . . . . . . . . . 126 UTOPIA Transmit Downstream Slave Mode . . . . . . . . . . . . . . . . . . . 126
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List of Figures Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 7-1 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 9-1 Page 135 136 136 137 144 339 340 341 342 343 345 345 350 351 353 354 356
Intel Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . Microprocessor Interface Write Cycle Timing (Intel) . . . . . . . . . . . . . Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . . . Microprocessor Interface Write Cycle Timing (Motorola) . . . . . . . . . . Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . . . Setup and Hold Time Definition (Single- and Multi-PHY). . . . . . . . . . Tristate Timing (Multi-PHY, Multiple Devices Only) . . . . . . . . . . . . . . SSRAM Interface Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . Generic SDRAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . Block Diagram of Test Access Port and Boundary Scan Unit . . . . . .
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List of Tables Table 2-1 Table 3-4 Table 3-17 Table 3-20 Table 3-24 Table 3-29 Table 3-30 Table 3-35 Table 3-38 Table 3-39 Table 3-40 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-8 Table 4-11 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 7-1 Table 7-2 Table 7-3 Table 7-5 Table 7-4 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12
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Ball Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Maximum ABM-3G Throughput and Speedup . . . . . . . . . . . . . . . . . . . 45 Threshold and Counter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Statistical Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Guaranteed Rates for each ATM Service Category . . . . . . . . . . . . . . 79 Summary of VBR Shaping Parameters . . . . . . . . . . . . . . . . . . . . . . . . 84 VBR Conformance Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timer Values for Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 AVT Context Table: VBR Shaping (Table Layout) . . . . . . . . . . . . . . . . 97 AVT Context Table: VBR Shaping Parameter Description . . . . . . . . . 97 Config(6:0) Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Scheduler Block Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SB Rate Calculation Examples for SYSCLK = 51.84 MHz . . . . . . . . 108 Minimum Shaper Rates as a Function of TstepC and SYSCLK . . . . 111 Shaper Accuracy as a Function of desired PCR and TstepC . . . . . . 112 Maximum BT as a Function of TstepC and SYSCLK . . . . . . . . . . . . 113 Number of Possible Connections per PHY . . . . . . . . . . . . . . . . . . . . 118 AAL5 Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Port/Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Port Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Standardized UTOPIA Level 2 Cell Format (16-bit) . . . . . . . . . . . . . . 130 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells . . . . 130 Standardized UTOPIA Level 2 Cell Format (16-bit) . . . . . . . . . . . . . . 131 Standardized UTOPIA Level 2 Cell Format (16-bit). . . . . . . . . . . . . . 131 Standardized UTOPIA Level 2 Cell Format (16-bit). . . . . . . . . . . . . . 132 Standardized UTOPIA Level 2 Cell Format (16-bit). . . . . . . . . . . . . . 132 External RAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SSRAM Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SDRAM Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 SSRAM and SDRAM Type Examples . . . . . . . . . . . . . . . . . . . . . . . . 141 Color Convention for Internal Table Field Illustration . . . . . . . . . . . . . 145 ABM-3G Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 External RAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 WAR Register Mapping for LCI Table Access . . . . . . . . . . . . . . . 191 Registers for LCI Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Registers for TCT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 WAR Register Mapping for TCT Table Access . . . . . . . . . . . . . . . . 196 Registers for Queue Configuration Table Access . . . . . . . . . . . . . . . 211 WAR Register Mapping for LCI Table Access . . . . . . . . . . . . . . . . . 212 Registers for SBOC Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 WAR Register Mapping for SBOC Table Access . . . . . . . . . . . . . . 224 Registers for MGT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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List of Tables Table 7-13 Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table 7-23 Table 7-24 Table 7-25 Table 7-26 Table 7-27 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table 8-7 Table 8-8 Table 8-9 Table 8-10 Table 8-11 Table 8-12 Table 8-13 Table 8-14 Table 8-15 Table 8-16 Table 8-18 Table 8-17 Page 231 247 247 248 251 251 252 257 258 267 267 268 280 281 292 336 336 337 339 340 341 342 343 346 346 347 348 350 351 353 354 355 355
WAR Register Mapping for MGT Table Access . . . . . . . . . . . . . . . . Registers for QPT1 Upstream Table Access . . . . . . . . . . . . . . . . . . . Registers for QPT1 Downstream Table Access . . . . . . . . . . . . . . . . WAR Register Mapping for QPT Table Access . . . . . . . . . . . . . . . . Registers for QPT2 Upstream Table Access . . . . . . . . . . . . . . . . . . . Registers for QPT2 Downstream Table Access . . . . . . . . . . . . . . . . WAR Register Mapping for QPT Table Access . . . . . . . . . . . . . . . . Registers SCTI Upstream Table Access . . . . . . . . . . . . . . . . . . . . . . Registers SCTI Downstream Table Access . . . . . . . . . . . . . . . . . . . . Registers SCTF Upstream Table Access . . . . . . . . . . . . . . . . . . . . . Registers SCTF Downstream Table Access . . . . . . . . . . . . . . . . . . . WAR Register Mapping for SCTFU/SCTFD Table access . . . . . . . Registers for AVT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAR Register Mapping for AVT Table Access . . . . . . . . . . . . . . . . Extended RAM Address Range for Test Access . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface Write Cycle Timing (Intel) . . . . . . . . . . . . . Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . . . Microprocessor Interface Write Cycle Timing (Motorola) . . . . . . . . . . Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . . . Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY). Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY) . Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Multi-PHY) . . Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Multi-PHY) . . SSRAM Interface AC Timing Characteristics. . . . . . . . . . . . . . . . . . . SDRAM Interface AC Timing Characteristics. . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Test Interface AC Timing Characteristics. . . . . . . . . Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Registers Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register 10 Register 11 Register 12 Register 13 Register 14 Register 15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 Register 22 Register 23 Register 24 Register 25 Register 26 Register 27 Register 28 Register 29 Register 30 Register 31 Register 32 Register 33 Register 34 Register 35 Register 36 Register 37 Register 38 Register 39 Register 40 Register 41 Register 42 Register 43 Register 44 Register 45 Register 46 Register 47 Register 48 Register 49 Register 50 Register 51 Page 156 157 158 160 162 163 164 165 166 168 170 171 172 174 175 176 178 179 180 181 181 183 184 185 186 187 188 189 190 192 193 194 198 201 204 207 213 214 217 219 220 221 222 225 226 227 228 229 232 233 234
UCFTST/DCFTST............................................................................... URCFG/DRCFG ................................................................................. UA5TXHD0/DA5TXHD0 ..................................................................... UA5TXHD1/DA5TXHD1 ..................................................................... UA5TXDAT0/DA5TXDAT0 ................................................................. UA5TXDAT1/DA5TXDAT1 ................................................................. UA5TXTR/DA5TXTR .......................................................................... UA5TXCMD/DA5TXCMD ................................................................... UA5RXHD0/DA5RXHD0..................................................................... UA5RXHD1/DA5RXHD1..................................................................... UA5RXDAT0/DA5RXDAT0................................................................. UA5RXDAT1/DA5RXDAT1................................................................. UA5SARS/DA5SARS ......................................................................... UBufferOcc/DBufferOcc ...................................................................... UBufferOccNg/DBufferOccNg............................................................. UBufMax/DBufMax ............................................................................. UMAC/DMAC ...................................................................................... UMIC/DMIC......................................................................................... CLP1DIS ............................................................................................. CONFIG .............................................................................................. UUBPTH0 ........................................................................................... UUBPTH1 ........................................................................................... UUBPTH2 ........................................................................................... UUBPTH3 ........................................................................................... UBPEI ................................................................................................. DUBPTH0 ........................................................................................... DUBPTH1 ........................................................................................... DUBPTH2 ........................................................................................... DUBPTH3 ........................................................................................... LCI0 .................................................................................................... LCI1 .................................................................................................... LCI2 .................................................................................................... TCT0 ................................................................................................... TCT1 ................................................................................................... TCT2 ................................................................................................... TCT3 ................................................................................................... QCT0 .................................................................................................. QCT1 .................................................................................................. QCT2 .................................................................................................. QCT3 .................................................................................................. QCT4 .................................................................................................. QCT5 .................................................................................................. QCT6 .................................................................................................. SBOC0 ................................................................................................ SBOC1 ................................................................................................ SBOC2 ................................................................................................ SBOC3 ................................................................................................ SBOC4 ................................................................................................ MGT0 .................................................................................................. MGT1 .................................................................................................. MGT2 ..................................................................................................
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List of Registers Register 52 Register 53 Register 54 Register 55 Register 56 Register 57 Register 58 Register 59 Register 60 Register 61 Register 62 Register 63 Register 64 Register 65 Register 66 Register 67 Register 68 Register 69 Register 70 Register 71 Register 72 Register 73 Register 74 Register 75 Register 76 Register 77 Register 78 Register 79 Register 80 Register 81 Register 82 Register 83 Register 84 Register 85 Register 86 Register 87 Register 88 Register 89 Register 90 Register 91 Register 92 Register 93 Register 94 Register 95 Register 96 Register 97 Register 98 Register 99 Register 100 Register 101 Register 102 Page 235 236 237 238 239 240 241 242 243 244 245 246 249 250 253 254 255 256 259 260 263 264 265 266 269 270 271 272 273 274 275 276 277 278 279 282 283 284 285 286 287 289 290 291 292 293 294 295 296 297 300
MASK0/MASK1................................................................................... MASK2/MASK3................................................................................... MASK4/MASK5................................................................................... MASK6 ................................................................................................ UCDV/DCDV....................................................................................... UQPTM0/DQPTM0 ............................................................................. UQPTM1/DQPTM1 ............................................................................. UQPTM2/DQPTM2 ............................................................................. UQPTM3/DQPTM3 ............................................................................. UQPTM4/DQPTM4 ............................................................................. UQPTM5/DQPTM5 ............................................................................. USCONF/DSCONF............................................................................. UQPT1T0/DQPT1T0........................................................................... UQPT1T1/DQPT1T1........................................................................... UQPT2T0/DQPT2T0........................................................................... UQPT2T1/DQPT2T1........................................................................... UQPT2T2/DQPT2T2........................................................................... UQPT2T3/DQPT2T3........................................................................... USADR/DSADR .................................................................................. USCTI/DSCTI ..................................................................................... UECRI/DECRI..................................................................................... UECRF/DECRF .................................................................................. UCRTQ/DCRTQ ................................................................................. USCTFM/DSCTFM ............................................................................. USCTFT/DSCTFT............................................................................... USCEN0/DSCEN0 .............................................................................. USCEN1/DSCEN1 .............................................................................. USCEN2/DSCEN2 .............................................................................. USCEN3/DSCEN3 .............................................................................. USCEN4/DSCEN4 .............................................................................. USCEN5/DSCEN5 .............................................................................. USCEN6/DSCEN6 .............................................................................. USCEN7/DSCEN7 .............................................................................. UCRTRI/DCRTRI ................................................................................ UCRTRF/DCRTRF ............................................................................. ERCT0 ................................................................................................ ERCT1 ................................................................................................ ERCM0 ............................................................................................... ERCM1 ............................................................................................... ERCCONF0 ........................................................................................ PLL1CONF ......................................................................................... PLLTST ............................................................................................... EXTRAMD0 ........................................................................................ EXTRAMD1 ........................................................................................ EXTRAMA0......................................................................................... EXTRAMA1......................................................................................... EXTRAMC .......................................................................................... VERL................................................................................................... VERH .................................................................................................. ISRU ................................................................................................... ISRD ...................................................................................................
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List of Registers Register 103 Register 104 Register 105 Register 106 Register 107 Register 108 Register 109 Register 110 Register 111 Register 112 Register 113 Register 114 Register 115 Register 116 Register 117 Register 118 Register 119 Register 120 Register 121 Register 122 Register 123 Register 124 Register 125 Register 126 Register 127 Page 303 304 305 306 307 309 311 312 315 317 319 320 321 322 323 324 325 327 329 330 331 332 333 334 335
ISRC ................................................................................................... IMRU ................................................................................................... IMRD ................................................................................................... IMRC ................................................................................................... MAR .................................................................................................... WAR.................................................................................................... USTATUS ........................................................................................... MODE1 ............................................................................................... MODE2 ............................................................................................... UTRXCFG........................................................................................... UUTRXP0 ........................................................................................... UUTRXP1 ........................................................................................... UUTRXP2 ........................................................................................... DUTRXP0 ........................................................................................... DUTRXP1 ........................................................................................... DUTRXP2 ........................................................................................... UUTTXCFG ........................................................................................ DUTTXCFG ........................................................................................ UUTTXP0............................................................................................ UUTTXP1............................................................................................ UUTTXP2............................................................................................ DUTTXP0............................................................................................ DUTTXP1............................................................................................ DUTTXP2............................................................................................ TEST ...................................................................................................
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ABM-3G PXF 4333 V1.1
Preface
The purpose of this Data Sheet is to provide comprehensive information about the ABM-3G device regarding system-level integration, hardware/board design, and software driver aspects. Organization of this Document This Data Sheet is divided into 13 chapters and two appendices. It is organized as follows: * Chapter 1, Overview Gives a general description of the product and its family, lists the key features, and presents some typical applications. * Chapter 2, Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes the signals. * Chapter 3, Functional Description Gives descriptions of major functional blocks, configuration tables, and global device functions. * Chapter 4, Operational Description Describes basic initialization and operation procedures. * Chapter 5, Interface Description Gives a functional description of all interfaces. * Chapter 6, Memory Structure * Chapter 7, Register Description Lists all registers and tables with functional description. * Chapter 8, Electrical Characteristics Provides detailed information about electrical characteristics and interface timings. * Chapter 9, Test Mode * Chapter 10, Package Outlines * Chapter 11, Glossary
Data Sheet
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2001-12-17
ABM-3G PXF 4333 V1.1
Related Documentation [1] [2] [3] [4] ITU-T Recommendation I.371, Traffic Control and Congestion Control in B-ISDN, 2nd Release, March 1996. ATMF, Traffic Management Specification 4.1, March 1999. ATMF, UTOPIA Level 1 Specification Version 2.01, March 1994. ATMF, UTOPIA Level 2 Specification Version 1, June 1995.
Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (ABM-3G), device part number (PXF 4333), device version (Version 1.1), and in the body of your e-mail: document type (Data Sheet), issue date (2001-12-17) and document revision number (DS 1).
Data Sheet
18
2001-12-17
ABM-3G PXF 4333 V1.1
Overview
1
Overview
The ABM-3G PXF 4333 Version 1.1 is Infineon's new generation ATM Buffer Manager device. It addresses the performance needs of new multi-service platforms with combined ATM cell and packet-handling applications. The ABM-3G manages ATM traffic flowing through multi-service platforms in which voice, video, and data traffic converge. The optimizes the interworking of ATM and higher-layer traffic-management and flow-control schemes. Optional "leaky bucket" shaping per queue provides full VBR support. The ABM-3G is useful in applications where extensive ATM traffic management capabilities are required. This includes either distributed or centralized system architectures that cover enterprise and Central Office switches, DSLAMs, and ATM line cards for routers and switches.
Data Sheet
19
2001-12-17
ATM Buffer Manager ABM-3G
ABM-3G PXF 4333 V1.1
1.1
Features
* ATM Traffic Management processing support up to STM-4/OC-12 equivalent bandwidth * Throughput at UTOPIA Interface up to 687 Mbit/s transmit, 795 Mbit/s receive * Speed-up factor relative to STM-4/OC12: 1.32 * Uni-directional mode with combined resources of both P-BGA-456 directions (optional) * 256K cells buffer per direction (configurable in guaranteed and shared buffer) * Up to 16384 connections arbitrarily assignable to queues for sharing connections and saving resources * Up to 8192 queues per direction, individually assignable to schedulers and to traffic classes * Up to 128 Scheduler Blocks (SB) per direction with programmable service rates, individually assignable to UTOPIA ports * The ABM-3G is cascadable to provide up to 512 schedulers, 32K queues, and 1M cell memories per direction * Up to 16 traffic classes with individually-selectable thresholds for highest service differentiation * Up to 48 ports per UTOPIA Interface * Standards-compliant support for the following ATM Forum service categories: CBR, rt-VBR, nrt-VBR, GFR, UBR, UBR+ * Generic PHB (Per Hop Behavior) characteristics are configurable (PHB traffic class is not standardized) * Configurable cell-address translation modes
*
1.1.1
Queueing Functions
* Per-VC queueing for up to 8192 connections per direction for optimal connection isolation
Type ABM-3G PXF 4333 V1.1
Data Sheet
Package BGA-456
20 2001-12-17
ABM-3G PXF 4333 V1.1
Overview * * * * Optional queue sharing Guaranteed per-queue minimum buffer reservation Cell acceptance based on programmable threshold sets with hysteresis evaluation Threshold sets for individual queues, traffic classes, schedulers, and global buffer for optimized buffer sharing * Per VC Packet Discard, including Early Packet Discard (EPD) & Partial Packet Discard (PPD) thresholds for Guaranteed Frame Rate (GFR) support * Cell Loss Priority (CLP) aware selective discard thresholds * UTOPIA input port backpressure thresholds without head-of-line-blocking
1.1.2
Scheduling Functions
* Multistage scheduling units with - Work conservative Weighted Round Robin (WRR) scheduling stage for 128 Scheduler Blocks - Each Scheduler Block comprising of - a Weighted Fair Queueing (WFQ) scheduler with 16320 programmable weight factors for each queue, providing rate guarantees and fairness in bandwidth allocation - a high priority Round Robin (RR) scheduler for real-time traffic - a low priority RR scheduler for best effort traffic * Additional common real-time bypass queue for each direction, for cascading multiple ABM-3Gs * Selectable Peak Cell Rate (PCR) shaping for each queue with minimum 2.62 Kbps and maximum 343 Mbit/s at 52 MHz clock (65472 programmable rates) * Selectable Variable Bit Rate (VBR.1.2.3) leaky bucket shaping for up to 2046 queues * VC merge function for up to 128 merge groups (arbitrary queues per merge group) for Multi Protocol Label Switching (MPLS) applications * SB scheduler overbooking possibility
1.1.3
Interfaces
* Two external SDRAM Interfaces for cell storage, one for upstream and one for downstream direction (up to 256 K cell buffer per direction) * One common cell pointer SSRAM Interface * Multiport UTOPIA Level 2 Interface in up- and downstream direction conforming to the specifications of the ATM Forum [4] - 4-cell FIFO buffer at UTOPIA receive interfaces for clock synchronization (head-of-line blocking-free) - 64-cell buffer logical queueing for up to 48 PHYs at UTOPIA transmit interfaces (head-of-line blocking-free) * 16-bit Microprocessor Interface, configurable as Intel or Motorola type (with AAL5 packet insertion/extraction support)
Data Sheet
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ABM-3G PXF 4333 V1.1
Overview * Queue Congestion Indication Interface * JTAG Boundary Scan Interface
1.1.4
Supervision Functions
* Internal pointer supervision * Cell-header protection function
1.1.5
* * * *
Technology
Supply voltages 1.8 V (core) and 3.3 V (I/Os) Ball Grid Array BGA-456 package (Plastic BGA (35 mm)2) Temperature range -40C to 85C Power dissipation 2.0 W (typical)
Data Sheet
22
2001-12-17
ABM-3G PXF 4333 V1.1
Overview
1.2
Logic Symbol
Cell Pointer RAM SSRAM Interface
Upstream Cell Storage RAM SDRAM Interface
UTOPIA L2 Interface (PHY Side)
UTOPIA L2 Interface (Backplane Side)
ABM-3G PXF 4333 V1.1
16 Bit uP Interface Bus
Figure 1-1
Logic Symbol
Data Sheet
Test/ JTAG/ Clocking IF
23
Downstream Cell Storage RAM SDRAM Interface
2001-12-17
ABM-3G PXF 4333 V1.1
Overview
1.3
Typical Applications
The ABM-3G device is designed for traffic management on line cards and trunk cards such as are used in: * * * *
*
ATM Switches DSLAMs, DLCs Multi-Service Access Switches 3G Wireless Infrastructure
ATM Cell Domain RAM ATM PHY
SSRAM SDRAM
ATM PHY
opt. ALP / AOP
ABM-P / ABM-3G
Bridge
Cell Backplane
RAM
ARC
SDRAM
Packet and Control Domain Bridge
Packet Backplane
TCV
RAM
Packet Controller
TCV
uP
Figure 1-2
General System Integration
Data Sheet
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2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions
2
2.1
*
Pin Descriptions
Pin Diagram
Bottom View
A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
URX PRTYU URX ENBU 1 URX ENBU 3 URX ADRU 1 URX ADRU 4 URX CLAVU 2 CSR RASU CSR ADRU 2 CSR ADRU 6 CSR ADRU 10 CSR DATU 1 VDD18 CSR DATU 8 CSR DATU 13 CSR DATU 18 CSR DATU 21 CSR DATU 26 CSR DATU 29 VSS TST ERC CLK TDI UTX ENBU 0 UTX ENBU 3 UTX ADRU 1 UTX ADRU 2 UTX ADRU 3
B
URX CLKU URX ENBU 2 URX ADRU 0 URX ADRU 2 VDD18 URX CLAVU 3 CSR CSU CSR ADRU 3 CSR ADRU 7 CSR ADRU 11 CSR DATU 2 CSR DATU 4 CSR DATU 9 CSR DATU 12 CSR DATU 17 CSR DATU 20 CSR DATU 25 CSR DATU 28 VSS
C
URX DATU 0 URX DATU 1 URX ENBU 0 URX ADRU 3 URX CLAVU 0 CSR WEU CSR ADRU 0 CSR ADRU 4 CSR ADRU 8 CSR BAU 1 CSR DATU 3 CSR DATU 5 CSR DATU 10 CSR DATU 11 CSR DATU 15 CSR DATU 19 CSR DATU 24 VDD18 CSR DATU 31 NC
D
URX DATU 2 URX DATU 3 NC
E
URX DATU 4 URX DATU 5 URX DATU 6 URX DATU 7 VSS
F
URX DATU 8 URX DATU 9 URX DATU 10 URX DATU 11 VSS
G
URX DATU 12 URX DATU 13 URX DATU 14 URX DATU 15 VDD33
H
VDD18
J
CPR ADR 18 CPR ADR 17 CPR ADR 16 CPR ADR 15 VSS
K
CPR ADR 14 CPR ADR 13 CPR ADR 12 CPR ADR 11 VSS
L
CPR ADR 10 CPR ADR 9 CPR ADR 8 NC
M
CPR ADR 7 CPR ADR 6 CPR ADR 5 CPR ADR 4 VDD33
N
CPR ADR 2 CPR ADR 1 CPR ADR 0 CPR ADR 3 VSS
P
CPR DAT 18 CPR DAT 19 VDD18 CPR DAT 17 VSS
R
CPR DAT 13 CPR DAT 14 CPR DAT 15 CPR DAT 16 VDD33
T
CPR DAT 10 CPR DAT 11 CPR DAT 12 CPR DAT 9 VDD33
U
CPR DAT 5 CPR DAT 6 CPR DAT 7 CPR DAT 8 VSS
V
CPR DAT 2 NC CPR DAT 3 CPR DAT 4 VSS
W
UTX DATD 15 VDD18 CPR DAT 0 CPR DAT 1 VDD33
Y
UTX DATD 11 UTX DATD 12 UTX DATD 13 UTX DATD 14 VDD33
AA
NC UTX DATD 8 UTX DATD 9 UTX DATD 10 VSS
AB
UTX DATD 4 UTX DATD 5 UTX DATD 6 UTX DATD 7 VSS
AC
UTX DATD 1 UTX DATD 2 UTX DATD 3 UTX CLAV3 UTX ENBD 2 CSR DATD 30 CSR DATD 26 CSR DATD 23 CSR DATD 19 CSR DATD 16 CSR DATD 15 CSR DATD 10 CSR DATD 8 CSR DATD 2 CSR DATD 1 CSR ADRD 8 CSR ADRD 7 CSR ADRD 3 CSR ADRD 0 CSR WED URX ENBD 1 URX ADRD 2 NC URX DATD 8 URX DATD 9 URX DATD 10
AD
NC UTX DATD 0 UTX SOCD UTX ADRD 1 UTX ENBD 3 CSR DATD 31 CSR DATD 27 CSR DATD 24 CSR DATD 20 CSR DATD 17 CSR DATD 12 CSR DATD 9 CSR DATD 5 CSR DATD 4 CSR DATD 0 CSR ADRD 11 CSR ADRD 6 CSR ADRD 2 CSR CSD
AE
UTX CLKD UTX PRTYD UTX ADRD 4 UTX ADRD 2 VDD18 UTX ENBD 0 CSR DATD 28 NC CSR DATD 21 NC CSR DATD 13 VDD18 CSR DATD 6 NC CSR BAD 0 CSR ADRD 10 CSR ADRD 5 CSR ADRD 1 CSR RASD URX ENBD 3 URX ADRD 4 URX ADRD 0 URX CLAVD 1 NC
AF
UTX CLAV2 UTX CLAV1 UTX CLAV0 UTX ADRD 3 UTX ADRD 0 UTX ENBD 1 CSR DATD 29 CSR DATD 25 CSR DATD 22 CSR DATD 18 CSR DATD 14 CSR DATD 11 CSR DATD 7 CSR DATD 3 CSR BAD 1 CSR ADRD 9 CSR ADRD 4 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CPR OE CPR GW CPR ADSC
URX SOCU URX CLAVU 1 CSR CASU CSR ADRU 1 CSR ADRU 5 CSR ADRU 9 CSR BAU 0 CSR DATU 0 CSR DATU 6 CSR DATU 7 CSR DATU 14 CSR DATU 16 CSR DATU 22 CSR DATU 23 CSR DATU 27 CSR DATU 30 NC
VDD33
VDD33
VSS
VSS
VDD33
VDD33
VDD33
VSS
Bottom View
VDD33
VSS
VSS
VSS
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VSS Signal Names: xxx: active high xxx: active low VSS: 0V VDD33: 3.3V VDD18: 1.8V Special Pin Type: oD: open Drain tri: TriState xxx signal name Internal Pull-Up Transistor Internal Pull-Down Transistor
VSS
VSS
VSS
VDD33
VDD33
CSR CASD URX ENBD 2 URX ADRD 3 URX CLAVD 3 URX CLAVD 0 URX PRTYD URX SOCD URX DATD 14
NC
VDD33
VDD33
VDD18 URX ENBD 0 URX ADRD 1 URX CLAVD 2 URX DATD 15 URX DATD 11 URX DATD 12
TRST
EXT FREEZE
RAM CLK
VSS
VSS
TDO UTX ENBU 2 UTX ADRU 0 UTX CLAVU 0 UTX CLAVU 1
TMS UTX ENBU 1 NC UTX CLAVU 3 UTX CLAVU 2
TCK UTX ADRU 4 UTX PRTYU UTX SOCU
VSS UTX DATU 2 UTX DATU 1 UTX DATU 0 UTX CLKU
VSS UTX DATU 6 UTX DATU 5 UTX DATU 4 UTX DATU 3
VDD33 UTX DATU 10 UTX DATU 9 UTX DATU 8 UTX DATU 7
VDD33 UTX DATU 14 UTX DATU 13 UTX DATU 12 UTX DATU 11 oD
VSS
VSS
VDD33
VDD33
VSS
VSS
VDD33
VDD33
VSS
VSS
VDD33
VDD33
VSS URX DATD 1 VDD18 URX DATD 2 URX DATD 3
VSS URX DATD 4 URX DATD 5 URX DATD 6 URX DATD 7
MP INT MP CS
MP RD MP WR tri MP RDY MP INTD
VSS
VDD18 PLL VSS PLL
VSS PLL SYS CLK SEL RESET
MP ADR2 SYS CLK MP ADR0 MP ADR1
VDD18
MP DAT1 MP ADR6 MP ADR7 MP DAT0
MP DAT2 MP DAT3 MP DAT4 MP DAT5
MP DAT6 MP DAT7 MP DAT8
MP DAT9 MP DAT10 MP DAT11 MP DAT12
MP DAT13 MP DAT14 MP DAT15 URX DATD 0
VSS
MP ADR3 MP ADR4 MP ADR5
MP MODE UTX DATU 15
VSS
VSS
URX CLKD URX DATD 13
oD
VDD18
NC
VSS
VDD18 PLL
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Figure 2-1
Pin Configuration (Bottom View)
Data Sheet
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2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions
2.2
*
Pin Diagram with Functional Groupings
Bottom View
UTOPIA Receive Upstream IF Cell Pointer SSRAM IF UTOPIA Transmit Downstream IF
A 1 2 3 4 5 6 7 8 9 10 11 12 13
Cell Storage SDRAM Upstrem IF
URX PRTYU URX ENBU 1 URX ENBU 3 URX ADRU 1 URX ADRU 4 URX CLAVU 2 CSR RASU CSR ADRU 2 CSR ADRU 6 CSR ADRU 10 CSR DATU 1 VDD18 CSR DATU 8 CSR DATU 13 CSR DATU 18 CSR DATU 21 CSR DATU 26 CSR DATU 29 VSS TST ERC CLK TDI UTX ENBU 0 UTX ENBU 3 UTX ADRU 1 UTX ADRU 2 UTX ADRU 3
B
URX CLKU URX ENBU 2 URX ADRU 0 URX ADRU 2 VDD18 URX CLAVU 3 CSR CSU CSR ADRU 3 CSR ADRU 7 CSR ADRU 11 CSR DATU 2 CSR DATU 4 CSR DATU 9 CSR DATU 12 CSR DATU 17 CSR DATU 20 CSR DATU 25 CSR DATU 28 VSS
C
URX DATU 0 URX DATU 1 URX ENBU 0 URX ADRU 3 URX CLAVU 0 CSR WEU CSR ADRU 0 CSR ADRU 4 CSR ADRU 8 CSR BAU 1 CSR DATU 3 CSR DATU 5 CSR DATU 10 CSR DATU 11 CSR DATU 15 CSR DATU 19 CSR DATU 24 VDD18 CSR DATU 31 NC
D
URX DATU 2 URX DATU 3 NC
E
URX DATU 4 URX DATU 5 URX DATU 6 URX DATU 7 VSS
F
URX DATU 8 URX DATU 9 URX DATU 10 URX DATU 11 VSS
G
URX DATU 12 URX DATU 13 URX DATU 14 URX DATU 15 VDD33
H
VDD18
J
CPR ADR 18 CPR ADR 17 CPR ADR 16 CPR ADR 15 VSS
K
CPR ADR 14 CPR ADR 13 CPR ADR 12 CPR ADR 11 VSS
L
CPR ADR 10 CPR ADR 9 CPR ADR 8 NC
M
CPR ADR 7 CPR ADR 6 CPR ADR 5 CPR ADR 4 VDD33
N
CPR ADR 2 CPR ADR 1 CPR ADR 0 CPR ADR 3 VSS
P
CPR DAT 18 CPR DAT 19 VDD18 CPR DAT 17 VSS
R
CPR DAT 13 CPR DAT 14 CPR DAT 15 CPR DAT 16 VDD33
T
CPR DAT 10 CPR DAT 11 CPR DAT 12 CPR DAT 9 VDD33
U
CPR DAT 5 CPR DAT 6 CPR DAT 7 CPR DAT 8 VSS
V
CPR DAT 2 NC CPR DAT 3 CPR DAT 4 VSS
W
UTX DATD 15 VDD18 CPR DAT 0 CPR DAT 1 VDD33
Y
UTX DATD 11 UTX DATD 12 UTX DATD 13 UTX DATD 14 VDD33
AA
NC UTX DATD 8 UTX DATD 9 UTX DATD 10 VSS
AB
UTX DATD 4 UTX DATD 5 UTX DATD 6 UTX DATD 7 VSS
AC
UTX DATD 1 UTX DATD 2 UTX DATD 3 UTX CLAV3 UTX ENBD 2 CSR DATD 30 CSR DATD 26 CSR DATD 23 CSR DATD 19 CSR DATD 16 CSR DATD 15 CSR DATD 10 CSR DATD 8 CSR DATD 2 CSR DATD 1 CSR ADRD 8 CSR ADRD 7 CSR ADRD 3 CSR ADRD 0 CSR WED URX ENBD 1 URX ADRD 2 NC URX DATD 8 URX DATD 9 URX DATD 10
AD
NC UTX DATD 0 UTX SOCD UTX ADRD 1 UTX ENBD 3 CSR DATD 31 CSR DATD 27 CSR DATD 24 CSR DATD 20 CSR DATD 17 CSR DATD 12 CSR DATD 9 CSR DATD 5 CSR DATD 4 CSR DATD 0 CSR ADRD 11 CSR ADRD 6 CSR ADRD 2 CSR CSD
AE
UTX CLKD UTX PRTYD UTX ADRD 4 UTX ADRD 2 VDD18 UTX ENBD 0 CSR DATD 28 NC CSR DATD 21 NC CSR DATD 13 VDD18 CSR DATD 6 NC CSR BAD 0 CSR ADRD 10 CSR ADRD 5 CSR ADRD 1 CSR RASD URX ENBD 3 URX ADRD 4 URX ADRD 0 URX CLAVD 1 NC
AF
UTX CLAV2 UTX CLAV1 UTX CLAV0 UTX ADRD 3 UTX ADRD 0 UTX ENBD 1 CSR DATD 29 CSR DATD 25 CSR DATD 22 CSR DATD 18 CSR DATD 14 CSR DATD 11 CSR DATD 7 CSR DATD 3 CSR BAD 1 CSR ADRD 9 CSR ADRD 4 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Cell Storage SDRAM Downstrem IF
CPR OE CPR GW CPR ADSC
URX SOCU URX CLAVU 1 CSR CASU CSR ADRU 1 CSR ADRU 5 CSR ADRU 9 CSR BAU 0 CSR DATU 0 CSR DATU 6 CSR DATU 7 CSR DATU 14 CSR DATU 16 CSR DATU 22 CSR DATU 23 CSR DATU 27 CSR DATU 30 NC
VDD33
VDD33
VSS
VSS
VDD33
VDD33
VDD33
VSS
Bottom View
VDD33
VSS
VSS
VSS
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 15 16 17 18 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VSS Signal Names: xxx: active high xxx: active low VSS: 0V VDD33: 3.3V VDD18: 1.8V
VSS
VSS
Special Pin Type: oD: open Drain tri: TriState xxx signal name Internal Pull-Up Transistor Internal Pull-Down Transistor
VSS
VDD33
VDD33
CSR CASD URX ENBD 2 URX ADRD 3 URX CLAVD 3 URX CLAVD 0 URX PRTYD URX SOCD URX DATD 14
Test IF
20 21 22 23 24 25 26
NC
VDD33
VDD33
VDD18 URX ENBD 0 URX ADRD 1 URX CLAVD 2 URX DATD 15 URX DATD 11 URX DATD 12
TRST
EXT FREEZE
RAM CLK
VSS
VSS
TDO UTX ENBU 2 UTX ADRU 0 UTX CLAVU 0 UTX CLAVU 1
TMS UTX ENBU 1 NC UTX CLAVU 3 UTX CLAVU 2
TCK UTX ADRU 4 UTX PRTYU UTX SOCU
VSS UTX DATU 2 UTX DATU 1 UTX DATU 0 UTX CLKU
VSS UTX DATU 6 UTX DATU 5 UTX DATU 4 UTX DATU 3
VDD33 UTX DATU 10 UTX DATU 9 UTX DATU 8 UTX DATU 7
VDD33 UTX DATU 14 UTX DATU 13 UTX DATU 12 UTX DATU 11 oD
VSS
VSS
VDD33
VDD33
VSS
VSS
VDD33
VDD33
VSS
VSS
VDD33
VDD33
VSS URX DATD 1 VDD18 URX DATD 2 URX DATD 3
VSS URX DATD 4 URX DATD 5 URX DATD 6 URX DATD 7
MP INT MP CS
MP RD MP WR tri MP RDY MP INTD
VSS
VDD18 PLL VSS PLL
VSS PLL SYS CLK SEL RESET
MP ADR2 SYS CLK MP ADR0 MP ADR1
VDD18
MP DAT1 MP ADR6 MP ADR7 MP DAT0
MP DAT2 MP DAT3 MP DAT4 MP DAT5
MP DAT6 MP DAT7 MP DAT8
MP DAT9 MP DAT10 MP DAT11 MP DAT12
MP DAT13 MP DAT14 MP DAT15 URX DATD 0
VSS
MP ADR3 MP ADR4 MP ADR5
MP MODE UTX DATU 15
VSS
VSS
URX CLKD URX DATD 13
oD
VDD18
NC
VSS
VDD18 PLL
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
UTOPIA Transmit Upstream IF
uP IF and Clock Supply IF
UTOPIA Receive Downstream IF
Figure 2-2
Pin Configuration (Bottom View)
Data Sheet
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2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions
2.3
Pin Definitions and Functions
Table 2-1 lists and explains all pins/balls organized into functional groups. Table 2-1 uses the following naming conventions: Ball No. Symbol Type Ball Number with respect to package outline (see Figure 2-1) Signal Name Type of pin/ball: I IPD IPU O O (oD) O (tri) Function Input pin Input pin (Internal Pull-Down Transistor) Input pin (Internal Pull-Up Transistor) Output pin (Push/Pull) Output pin (Open Drain) Output pin (TriState)
Functional pin/ball description
Note: The ABM-3G signal pins are not 5 V I/O tolerant. For further details refer to "DC Characteristics" on Page 337. Table 2-1 Ball No. Ball Definitions and Functions Type Function
Symbol
2.3.1
P24
Common System Clock Supply (3 pins)
SYSCLK I System Clock This clock signal feeds DPLL1 and DPLL2 and the internal ABM-3G Core Clock, depending on signal SYSCLKSEL. Internal ABM-3G Core Clock Source Select: 'H': Internal Core Clock is supplied by signal SYSCLK 'L': Internal Core Clock is supplied by DPLL1
N24
SYSCLKSEL
IPD
Data Sheet
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. D21 Ball Definitions and Functions (cont'd) Type O Function Reference clock for external RAM (CSRU, CSRD and CPR)
Symbol RAMCLK
2.3.2
G4, G3, G2, G1, F4, F3, F2, F1, E4, E3, E2, E1, D2, D1, C2, C1 A1 A5, C4, B4, A4, B3 A3, B2, A2, C3
UTOPIA Receive Interface Upstream (Master/Slave) (32 pins)
15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 I UTOPIA Receive Data Bus Upstream (from PHY)
URXPRTYU 4, 3, 2, 1, 0 3, 2, 1, 0 URXENBU(3:0) URXADRU(4:0)
URXDATU(15:0) IPD I/O PD
UTOPIA Receive Odd Parity of URXDATU(15:0) (PHY side) UTOPIA Receive Address Bus (PHY side) Master Mode: output Slave Mode: input
I/O PU
UTOPIA Receive Enable Bus (PHY side) Master Mode: output Slave Mode: input
Data Sheet
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. B6, A6, D5, C5 Ball Definitions and Functions (cont'd) Type URXCLAVU(3:0) I/O PD Function UTOPIA Receive CLAV Bus (PHY side) Master Mode: input Slave Mode: output
Symbol 3, 2, 1, 0
D4 B1
URXSOCU URXCLKU
IPD I
UTOPIA Receive Start of Cell signal (PHY side) UTOPIA Receive Clock signal (PHY side)
2.3.3
W1, Y4, Y3, Y2, Y1, AA4, AA3, AA2, AB4, AB3, AB2, AB1, AC3, AC2, AC1, AD2 AE2
UTOPIA Transmit Interface Downstream (Master/Slave) (32 pins)
15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 O UTOPIA Transmit Data Bus Downstream (to PHY)
UTXPRTYD
UTXDATD(15:0) OPD
UTOPIA Transmit Odd Parity of UTXDATD(15:0) (PHY side)
Data Sheet
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2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. AE3, AF4, AE4, AD4, AF5 AD5, AC5, AF6, AE6 Ball Definitions and Functions (cont'd) Type UTXCLAVD(3:0) UTXENBD(3:0) UTXADRD(4:0) I/O PD Function UTOPIA Transmit Address Bus (PHY side) Master Mode: output Slave Mode: input
Symbol 4, 3, 2, 1, 0 3, 2, 1, 0
I/O PU
UTOPIA Transmit Enable Bus (PHY side) Master Mode: output Slave Mode: input
AC4, AF1, AF2, AF3
3, 2, 1, 0
I/O PD
UTOPIA Transmit CLAV Bus (PHY side) Master Mode: input Slave Mode: output
AD3 AE1
UTXSOCD UTXCLKD
OPD I
UTOPIA Transmit Start of Cell signal (PHY side) UTOPIA Transmit Clock signal (PHY side)
Data Sheet
30
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. Ball Definitions and Functions (cont'd) Type Function
Symbol
2.3.4
AD24, AF26, AE26, AD26, AD25, AC26, AC25, AC24, AB26, AB25, AB24, AB23, AA26, AA25, AA23, Y26 AF24 AE21, AF21, AC22, AD22, AE22 AE20, AF20, AC21, AD21
UTOPIA Receive Interface Downstream (Master/Slave) (32 pins)
15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 I UTOPIA Receive Data Bus Downstream (from Backplane)
URXPRTYD 4, 3, 2, 1, 0 3, 2, 1, 0 URXENBD(3:0) URXADRD(4:0)
URXDATD(15:0) IPD I/O PD
UTOPIA Receive Odd Parity of URXDATD(15:0) (Backplane side) UTOPIA Receive Address Bus (Backplane side) Master Mode: output Slave Mode: input
I/O PU
UTOPIA Receive Enable Bus (Backplane side) Master Mode: output Slave Mode: input
Data Sheet
31
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Pin Descriptions Table 2-1 Ball No. AF22, AD23, AE23, AF23 Ball Definitions and Functions (cont'd) Type URXCLAVD(3:0) I/O PD Function UTOPIA Receive CLAV Bus (Backplane side) Master Mode: input Slave Mode: output
Symbol 3, 2, 1, 0
AF25 AE25
URXSOCD URXCLKD
IPD I
UTOPIA Receive Start of Cell signal (Backplane side) UTOPIA Receive Clock signal (Backplane side)
2.3.5
J26, H23, H24, H25, H26, G23, G24, G25, G26, F23, F24, F25, F26, E23, E24, E25 D24
UTOPIA Transmit Interface Upstream (Master/Slave) (32 pins)
15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 O UTOPIA Transmit Data Bus Upstream (to Backplane)
UTXPRTYU
UTXDATU(15:0) OPD
UTOPIA Transmit Odd Parity of UTXDATU(15:0) (Backplane side)
Data Sheet
32
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. D23, A26, A25, A24, B24 A23, B23, C23, A22 Ball Definitions and Functions (cont'd) Type UTXCLAVU(3:0) UTXENBU(3:0) UTXADRU(4:0) I/O PD Function UTOPIA Transmit Address Bus (Backplane side) Master Mode: output Slave Mode: input
Symbol 4, 3, 2, 1, 0 3, 2, 1, 0
I/O PU
UTOPIA Transmit Enable Bus (Backplane side) Master Mode: output Slave Mode: input
C25, C26, B26, B25
3, 2, 1, 0
I/O PD
UTOPIA Transmit CLAV Bus (Backplane side) Master Mode: input Slave Mode: output
D25 E26
UTXSOCU UTXCLKU
OPD I
UTOPIA Transmit Start of Cell signal (Backplane side) UTOPIA Transmit Clock signal (Backplane side)
2.3.6
N25
Microprocessor Interface (32 pins)
RESET I ABM-3G Reset
Data Sheet
33
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. Y25, Y24, Y23, W26, W25, W24, W23, V25, V24, V23, U26, U25, U24, U23, T23, T26 T25, T24, R26, R25, R24, P23, P26, P25 K24 K23 J24 J23 Ball Definitions and Functions (cont'd) Type I/O Function Microprocessor Data Bus
Symbol 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 7, 6, 5, 4, 3, 2, 1, 0 MPWR MPRD MPCS MPINT
MPDAT(15:0) I MPADR(7:0)
Microprocessor Address Bus
I I I O(oD)
WR when MPMOD=0 (Intel Mode) R/W when MPMOD=1 (Motorola Mode). RD when MPMOD=0 (Intel Mode) DS when MPMOD=1 (Motorola Mode). Chip Select from Microprocessor. Interrupt Request to Microprocessor. Open drain, needs external pull-up resistor. Interrupt pins of several devices can be wired-or together. Ready Output to Microprocessor for read and write accesses.
K25
MPRDY
O(tri)
Data Sheet
34
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. J25 Ball Definitions and Functions (cont'd) Type IPD Function Intel/Motorola select: 'L' Intel type processor 'H' Motorola type processor
Symbol MPMODE
2.3.7
C19, D19, A18, B18, D18, A17, B17, C17, D17, D16, A16, B16, C16, A15, B15, D15, C15, D14, A14, B14, C14, C13, B13, A13, D13, D12, C12, B12, C11, B11, A11, D11
Cell Storage RAM Upstream (50 pins)
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 I/O Data Bus to Cell Storage RAM Upstream
Data Sheet
CSRDATU(31:0)
35
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Pin Descriptions Table 2-1 Ball No. D10 C10 B10, A10, D9, C9, B9, A9, D8, C8, B8, A8, D7, C7 B7 A7 D6 C6 Ball Definitions and Functions (cont'd) Type O O O CSRADRU(11:0) Function Cell Storage RAM Bank Address 0 Upstream Cell Storage RAM Bank Address 1 Upstream Address Bus of Cell Storage RAM Upstream
Symbol CSRBAU0 CSRBAU1 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
CSRCSU CSRRASU CSRCASU CSRWEU
O O O O
Cell Storage RAM Upstream Chip Select Cell Storage RAM Upstream Row Address Strobe Cell Storage RAM Upstream Column Address Strobe Cell Storage RAM Upstream Write Enable
Data Sheet
36
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. Ball Definitions and Functions (cont'd) Type Function
Symbol
2.3.8
AD6, AC6, AF7, AE7, AD7, AC7, AF8, AD8, AC8, AF9, AE9, AD9, AC9, AF10, AD10, AC10, AC11, AF11, AE11, AD11, AF12, AC12, AD12, AC13, AF13, AE13, AD13, AD14, AF14, AC14, AC15, AD15 AE15
Cell Storage RAM Downstream (50 pins)
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 I/O Data Bus to Cell Storage RAM Downstream
CSRBAD0
CSRDATD(31:0) O
Cell Storage RAM Bank Address 0 Downstream
Data Sheet
37
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. AF15 AD16, AE16, AF16, AC16, AC17, AD17, AE17, AF17, AC18, AD18, AE18, AC19 AD19 AE19 AF19 AC20 Ball Definitions and Functions (cont'd) Type O O CSRADRD(11:0) Function Cell Storage RAM Bank Address 1 Downstream Address Bus of Cell Storage RAM Downstream
Symbol CSRBAD1 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
CSRCSD CSRRASD CSRCASD CSRWED
O O O O
Cell Storage RAM Downstream Chip Select Cell Storage RAM Downstream Row Address Strobe Cell Storage RAM Downstream Column Address Strobe Cell Storage RAM Downstream Write Enable
Data Sheet
38
2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. Ball Definitions and Functions (cont'd) Type Function
Symbol
2.3.9
P2, P1, P4, R4, R3, R2, R1, T3, T2, T1, T4, U4, U3, U2, U1, V4, V3, V1, W4, W3
Common Up- and Downstream Cell Pointer RAM (42 pins)
19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 I/O Data Bus to Cell Pointer RAM
Data Sheet
CPRDAT(19:0)
39
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ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. J1, J2, J3, J4, K1, K2, K3, K4, L1, L2, L3, M1, M2, M3, M4, N4, N1, N2, N3 H4 H3 H2 Ball Definitions and Functions (cont'd) Type O Function Address Bus of Cell Pointer RAM
Symbol 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
CPRADSC CPRGW CPROE
CPRADR(18:0) O O O
Cell Pointer RAM Chip Select Cell Pointer RAM Write Enable Cell Pointer RAM Output Enable
2.3.10
A21 D22 C22 B21 B22
JTAG Boundary Scan (5 pins)
TDI TCK TMS TRST TDO IPU I I
PU
Test Data Input. Test Clock. Test Mode Select. Test Data Reset Test Data Output In normal operation, must not be connected.
IPU
PU
O
Data Sheet
40
2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. Ball Definitions and Functions (cont'd) Type Function
Symbol
2.3.11
A20 C21
Production Test (2 pin)
TSTERCCLK EXTFREEZ IPD IPD For device test only, do not connect. Must not be connected in normal operation. For device test only, do not connect. Must not be connected in normal operation.
2.3.12
Supply (74 VSS, 32 VDD33 and 14 VDD18 pins)
A19, B19, E5, E6, E9, E10, E13, VSS, Chip GND Supply E14, E17, E18, E21, E22, F5, F22, (All pins should be connected to the same level) J5, J22, K5, K22, L11, L12, L13, L14, L15, L16, L23, L24, L25, M11, M12, M13, M14, M15, M16, M25, M26, N5, N11, N12, N13, N14, N15, N16, N22, P5, P11, P12, P13, P14, P15, P16, P22, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, U5, U22, V5, V22, AA5, AA22, AB5, AB6, AB9, AB10, AB13, AB14, AB17, AB18, AB21, AB22 E7, E8, E11, E12, E15, E16, E19, VDD33, Chip 3.3 V Supply E20, G5, G22, H5, H22, L5, L22, (All pins should be connected to the same level) M5, M22, R5, R22, T5, T22, W5, W22, Y5, Y22, AB7, AB8, AB11, AB12, AB15, AB16, AB19, AB20 B5, A12, C18, D26, R23, AA24, AD20, AE12, AE5, W2, P3, H1 N23, M24 N26, M23 VDD18, Chip 1.8 V Supply (All pins should be connected to the same level) VSS PLL, Chip GND Supply (All pins should be connected to the same level) VDD18 PLL, Chip 1.8 V Supply (All pins should be connected to the same level)
Data Sheet
41
2001-12-17
ABM-3G PXF 4333 V1.1
Pin Descriptions Table 2-1 Ball No. Ball Definitions and Functions (cont'd) Type Function
Symbol
2.3.13
Unconnected (13 pins)
B20, C20, D20, L26, K26, D3, L4, Unconnected pins. V2, AA1, AD1, AE8, AE10, AE14, It is recommended to leave these pins unconnected on the board to guarantee board compatibility to AF18, AE24, AC23, V26, C24 future device versions. Note: Total signal pins: 323; total power supply pins: 120.
Data Sheet
42
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ABM-3G PXF 4333 V1.1
Functional Description
3
3.1
Functional Description
Block Diagrams
Figure 3-1 shows a typical sub-system integration scenario using the ABM-3G. The memory configurations are examples and depend on the ABM-3G operation modes and required queueing resources.
*
Cell Pointer RAM
. ..
Upstream Cell Storage RAM
... . ..
512K*32
4M*16 4M*16
. ..
.. .
...
...
...
...
...
UTOPIA L2 Interface (PHY Side)
PXF 4333 ABM-3G
...
16 Bit uP Interface Bus
Test/ JTAG/ Clocking IF
...
Downstream Cell Storage RAM
Figure 3-1
Sub-System Integration Diagram
Figure 3-2 shows a functional block diagram of the ABM-3G. The function blocks are referenced and described in more detail in subsequent chapters.
Data Sheet
43
. ..
.. .
.. .
.. .
UTOPIA L2 Interface (Backplane Side)
.. . .. .
4M*16 4M*16
... ...
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
*
14
42
50
Buffer Manager AAL5
Queue Scheduler
UTOPIA Interface (Backplane Side)
UTOPIA Interface (PHY Side)
687 Mbit/s (53 Byte, 51.84 MHz)
Test/ Clocks
SSRAM IF
ARC
SDRAM Interface (up) Cell Handler upstream
687 Mbit/s (53 byte, 51.84MHz)
64
64
687 Mbit/s (53 byte, 51.84MHz)
687 Mbit/s (53 Byte, 51.84 MHz)
Cell Handler downstream BSCAN
5
ARC
uP IF
32
SDRAM Interface (dn)
50
Figure 3-2
Functional Block Diagram
Figure 3-3 shows a logical illustration of the ATM Buffer Manager (ABM-3G) core for one direction. Cells are assigned to queues in the Buffer Manager unit. The cell acceptance algorithm verifies that no thresholds are exceeded that are provided for queues, schedulers, traffic classes, as well as for the global buffer. Once accepted, a cell cannot be lost, but will be emitted at the respective UTOPIA Interface after some time (exception: queue has been disabled while cells are stored). Alternatively, cells can be received from the Microprocessor Interface via the AAL5 unit. The demultiplexer forwards the cells to the respective queue associated with a scheduler which sorts them for transmission according to the programmed configuration. As part of the scheduling function, an optional Peak Rate Limiter and a Leaky-Bucket shaper are provided for the shaping of individual queues (connections). The Queue Scheduler and the Buffer Manager are the key units for QoS provisioning in the ABM-3G. The behavior of both units is described in subsequent chapters. The output multiplexer recombines the cell streams of all schedulers. Emitted cells are either forwarded to the UTOPIA Transmit Interface or to the AAL5 unit for extraction.
Data Sheet
44
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Functional Description
Empty Cell Cycles
ARC
Buffer Manager Cell Acceptance Algorithm
Global Real Time Bypass Scheduler Block #127 Scheduler Block #1 Scheduler Block #0 D E M U X W F Q
Address Reduction
cells in
cells out
S B S
AAL5 Assistant
uP Interface
Scheduler Rate Shaping Cyclic Mux WFQ Weighted Fair Queueing Scheduler Strict Priority Mux
Figure 3-3
Logical Block Diagram (One Direction)
3.1.1
Throughput and Speedup
At a given clock frequency, applied to the ABM-3G UTOPIA interfaces and the ABM-3G core, the core is the limiting factor for throughput because it needs 32 clock cycles per cell as opposed to UTOPIA, which needs only 27+2. The available speedup in the ABM-3G relative to STM-4/OC12 transmission rates is shown in Table 3-4. Table 3-4 Clock Frequency 51.84 Maximum ABM-3G Throughput and Speedup ABM-3G core Throughput Speedup relative to STM-4/OC12 (599.04 Mbit/s) [Mbit/s] (53 Byte Cells) 686.88 1.146
Data Sheet
45
2001-12-17
uP Interface
Queue with Shaping Function
AAL5 Assistant
UTOPIA Transmit
UTOPIA Receive
ABM-3G PXF 4333 V1.1
Functional Description
3.2 3.2.1
Functional Block Description Cell Handler (Upstream/Downstream)
The Cell Handler (CH) units are responsible for the physical data flow of storing and retrieving cells to/from the respective Cell Storage RAM or insertion and extraction of Resource Management (RM) cells. Updates to the cell header section or to the cell contents in case of OAM-RM cells are also performed by the Cell Handler units.
3.2.2
Buffer Manager and Queue Scheduler (Overview)
The Buffer Manager (BM) unit is the central function of the ABM-3G device and handles the logical data flows for upstream and downstream direction. It utilizes the Queue Scheduler to coordinate cell emission and a common Cell Pointer RAM (SSRAM) to administrate cell storage. Any cell entering the CH unit is reported to the BM unit running the cell acceptance algorithm. In a first step a cell is classified and associated to the logical resource entities connection, queue, traffic class and scheduler. Once all associated resources are determined, the BM runs the cell acceptance algorithm based on the current parameter sets. As a result of all threshold evaluations the cell is either discarded or accepted and related counters are updated accordingly. Non-empty queues are reported to the Queue Scheduler (QS) unit to be scheduled by the associated calendar. In return the QS unit reports queues to the Buffer Manager that are due for cell transmission in the current cell slot. Upon a cell emit request for a specific queue the BM requests the Cell Handler to retrieve and transmit the next cell. Since the BM and QS units are the central functions of the ABM-3G device they are described in more detail in chapter "Buffer Manager and Queue Scheduler Details" on Page 60.
3.2.3
AAL5 Assistant
The AAL5 Assistant unit allows insertion and extraction of AAL5 segmented packets from and towards the Microprocessor Interface. Supported by the corresponding software driver, the unit implements an "in-line" SAR function, i.e. one packet is processed at any time by an SAR function. However, upstream and downstream flow as well as extraction and insertion are independent functions that may be operationally interleaved. For extraction, a Scheduler Block must be associated to the AAL5 Assistant unit and each queue assigned to this scheduler block must be assigned to a VC-merge group to guarantee that complete packets are forwarded to the AAL5 Assistant unit. The scheduler block rates can be adjusted according to the microprocessor interface bandwidth or the intended CPU load. However, the CPU may extract the payload chunks at a lower rate which will result in internal scheduler block backpressure. No data loss
Data Sheet 46 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description will occur in that case. The CPU reads consecutive bytes from the cell's payload chunks that can be re-assembled immediately in the host memory while the AAL5 Assistant unit checks the AAL5 trailer. The section "AAL5 Packet Extraction" on Page 121 provides programming details. Refer to "Scheduler Configuration Table Integer Transfer Registers" on Page 257 for the assignment of scheduler blocks to the AAL5 Assistant and the programming of their rates. For insertion, the CPU prepares the ATM cell header for the following packet and writes packet payload chunks to the AAL5 Assistant unit which will generate the cells and the AAL5 trailer for automatic completion of the last cell of the packet. Internally, the cells are forwarded to either the downstream or upstream Cell Handler and processed in the same way as cells received by an UTOPIA receive interface. The section "AAL5 Packet Insertion" on Page 121 provides the details.
3.2.4
Internal Address Reduction Unit
The ABM-3G requires an internal 16-bit Local Connection Identifier (LCI) to address its resources. Two basic cell addressing schemes are supported to extract/generate an LCI from the cell header: * LCI Mapping Modes An external device generates an LCI and maps it into the ATM cell header. Three different mapping modes are supported by the ABM-3G. The LCI mapping modes are described as part of the UTOPIA interface description in chapters "UTOPIA L2 Interfaces (PHY side)" on Page 124 and "UTOPIA L2 Interface (Backplane side)" on Page 134. * Internal Address Reduction Mode The ABM-3G generates its own internal LCI as a programmable combination of the cell header fields VPI, VCI and the Port Number (PN). The port number is taken either from the UTOPIA port number or the UDF1 cell header byte. Internal Address Reduction Two parameters in Register 111 "MODE2" on Page 315 determine the building function of the internal LCI value: * PNUM(2:0) Determines the number of bits taken from the port number field. * MNUM(3:0) Determines the VCI and VPI ranges depending on the cell header VPI value. Two translation functions are effective, depending on the cell header VPI(11:0) value compared to the configured parameter MNUM.
Data Sheet
47
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ABM-3G PXF 4333 V1.1
Functional Description In the first case i x = 16 - MNUM x VPI (11,0) < 2 - 1 ; with i ix = 0 for for MNUM > 0 u y MNUM = 0
the LCI is built by {VPI, VCI, PN} values whereas the VCI range is given by (MNUM - PNUM) bits and the VPI range is given by (16 - MNUM) bits. Note: Programming MNUM(3:0) = 0 is interpreted as decimal 16. The following tables provide the possible LCI building patterns for all allowed PNUM and MNUM configurations. The resulting LCI is internally treated in the same way as in the LCI cell header mapping modes, i.e. the two MSBs are checked against the quarter segment configuration that allows for cascading of up to four ABM-3G devices. Note: VPI and VCI cell header field positions that are not mapped into the LCI are checked against `0'. A mismatch is treated as `invalid LCI' and the cell is discarded.
Data Sheet
48
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ABM-3G PXF 4333 V1.1
Functional Description
*
PNUM MNUM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 8 VPI(7:0) VCI(7:0) 0 9 VPI(6:0) VCI(8:0) 0 10 VPI(5:0) VCI(9:0) 0 11 VPI(4:0) VCI(10:0) 0 12 VPI(3:0) VCI(11:0) 1 9 PN VCI(7:0) VPI(6:0) 1 10 PN VPI(5:0) VCI(8:0) 1 11 PN VPI(4:0) VCI(9:0) 1 12 PN VPI(3:0) VCI(10:0) 1 13 PN VPI(2:0) VCI(11:0) 1 14 PN VPI(1:0) VCI(12:0) 1 15 VPI PN VCI(13:0) 1 16 PN VCI(14:0) 2 9 VPI(6:0) VCI(6:0) PN(1:0) 2 10 VPI(5:0) VCI(7:0) PN(1:0) 2 11 VCI(8:0) PN(1:0) VPI(4:0) 2 12 VPI(3:0) VCI(9:0) PN(1:0) 2 13 VPI(2:0) VCI(10:0) PN(1:0) 2 14 VPI(1:0) VCI(11:0) PN(1:0) 2 15 VPI VCI(12:0) PN(1:0) 2 16 VCI(13:0) PN(1:0) 3 10 PN(2:0) VCI(6:0) VPI(5:0) 3 11 VCI(7:0) PN(2:0) VPI(4:0) 3 12 PN(2:0) VPI(3:0) VCI(8:0) 3 13 PN(2:0) VPI(2:0) VCI(9:0) 3 14 VPI(1:0) PN(2:0) VCI(10:0) 3 15 VPI PN(2:0) VCI(11:0) 3 16 PN(2:0) VCI(12:0) 4 10 PN(3:0) VCI(5:0) VPI(5:0) 4 11 PN(3:0) VPI(4:0) VCI(6:0) 4 12 VPI(3:0) VCI(7:0) PN(3:0) 4 13 PN(3:0) VPI(2:0) VCI(8:0) 4 14 VCI(9:0) PN(3:0) VPI(1:0) 4 15 VPI PN(3:0) VCI(10:0) 4 16 VCI(11:0) PN(3:0) 5 11 VPI(4:0) VCI(5:0) PN(4:0) 5 12 VPI(3:0) VCI(6:0) PN(4:0) 5 13 VPI(2:0) VCI(7:0) PN(4:0) 5 14 VPI(1:0) VCI(8:0) PN(4:0) 5 15 VPI VCI(9:0) PN(4:0) 5 16 VCI(10:0) PN(4:0) 6 12 PN(5:0) VCI(5:0) VPI(3:0) 6 13 PN(5:0) VCI(6:0) VPI(2:0) 6 14 VCI(7:0) VPI(1:0) PN(5:0) 6 15 VPI VCI(8:0) PN(5:0) 6 16 VCI(9:0) PN(5:0) 7 13 VPI(2:0) VCI(5:0) PN(6:0) 7 14 VCI(6:0) VPI(1:0) PN(6:0) 7 15 VPI PN(6:0) VCI(7:0) 7 16 VCI(8:0) PN(6:0)
Figure 3-5
LCI Building Patterns
Data Sheet
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ABM-3G PXF 4333 V1.1
Functional Description In the second case i x = 16 - MNUM x VPI (11,0) 2 - 1 ; with i ix = 0 for for MNUM > 0 u y MNUM = 0
the LCI is built by {VPI, PN} values only whereas the VPI range is given by MNUM bits. Note: Programming MNUM(3:0) = 0 is interpreted as decimal 16. The following tables provide the possible LCI building patterns for all PNUM and MNUM configurations. The resulting LCI is internally treated in the same way as in the LCI cell header mapping modes, i.e. the two MSBs are checked against the quarter segment configuration that allows for cascading of up to four ABM-3G devices. Note: VPI cell header field positions that are not mapped into the LCI are checked against `0'. A mismatch is treated as `invalid LCI' and the cell is discarded. Note: When QS check is enabled (for cascaded ABM-3Gs), the transparent VPCs are handled by the ABM-3G with QS=11b. See Register 111 "MODE2" on Page 315.
Data Sheet
50
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ABM-3G PXF 4333 V1.1
Functional Description
*
PNUM MNUM 15 0 8 1 0 9 1 0 10 1 0 11 1 0 12 1 1 9 1 1 10 1 1 11 1 1 12 1 1 13 1 1 14 1 1 15 1 1 16 2 9 1 2 10 1 2 11 1 2 12 1 2 13 1 2 14 1 2 15 1 2 16 3 10 1 3 11 1 3 12 1 3 13 1 3 14 1 3 15 1 3 16 4 10 1 4 11 1 4 12 1 4 13 1 4 14 1 4 15 1 4 16 5 11 1 5 12 1 5 13 1 5 14 1 5 15 1 5 16 6 12 1 6 13 1 6 14 1 6 15 1 6 16 7 13 1 7 14 1 7 15 1 7 16
14 1 1 1 1 1 1 1 1 1 1 1
13 1 1 1 1 1 1 1 1 1 1
12 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1
1 1 1 1 1
1 1 1 1
1 1 1 1
1 1 1
1 1 1
1 1
1 1
1
4 3 2 1 0 VPI(7:0) VPI(8:0) VPI(9:0) VPI(10:0) VPI(11:0) 1 1 1 PN VPI(7:0) 1 1 PN VPI(8:0) 1 PN VPI(9:0) PN VPI(10:0) PN VPI(11:0) PN VPI(12:0) PN VPI(13:0) PN VPI(14:0) 1 1 1 1 VPI(6:0) PN(1:0) 1 1 1 PN(1:0) VPI(7:0) 1 1 VPI(8:0) PN(1:0) 1 VPI(9:0) PN(1:0) VPI(10:0) PN(1:0) VPI(11:0) PN(1:0) VPI(12:0) PN(1:0) VPI(13:0) PN(1:0) 1 1 1 VPI(6:0) PN(2:0) 1 1 VPI(7:0) PN(2:0) 1 VPI(8:0) PN(2:0) VPI(9:0) PN(2:0) VPI(10:0) PN(2:0) VPI(11:0) PN(2:0) VPI(12:0) PN(2:0) 1 1 1 VPI(5:0) PN(3:0) 1 1 VPI(6:0) PN(3:0) 1 VPI(7:0) PN(3:0) VPI(8:0) PN(3:0) VPI(9:0) PN(3:0) VPI(10:0) PN(3:0) VPI(11:0) PN(3:0) 1 1 VPI(5:0) PN(4:0) 1 PN(4:0) VPI(6:0) PN(4:0) VPI(7:0) VPI(8:0) PN(4:0) VPI(9:0) PN(4:0) VPI(10:0) PN(4:0) 1 VPI(5:0) PN(5:0) VPI(6:0) PN(5:0) VPI(7:0) PN(5:0) VPI(8:0) PN(5:0) PN(5:0) VPI(9:0) VPI(5:0) PN(6:0) VPI(6:0) PN(6:0) VPI(7:0) PN(6:0) VPI(8:0) PN(6:0)
11 1 1 1 1
10 1 1 1
9 1 1
8 1
7
6
5
Figure 3-6
LCI Building Patterns (VPI only)
Data Sheet
51
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
3.2.5
Clocking System
The clocking system of the ABM-3G distinguishes the core clock and the UTOPIA Interfaces whereas each UTOPIA Interface and direction (transmit/receive) is clocked independently, as shown in Figure 3-7.
3.2.5.1
Clocking System Overview
Divider2
Bypass1
Divider1
DPLL1
internal ABM-3G core clock
SYSCLKSEL
URXCLKU
UTXCLKD
Note: Testmodes are not illustrated in this figure.
Figure 3-7
Clocking System Overview
Data Sheet
SYSCLK
52
URXCLKD
UTXCLKU
UTOPIA backplane receive
UTOPIA PHY transmit
ABM-3G Core Logic
UTOPIA backplane transmit
UTOPIA PHY receive
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
3.2.5.2
DPLL Programming
The DPLL features two factors programmed by parameters m and n in register "PLL1CONF" on Page 287 :
f 1 = f in ( m + 1 )
;
n+1 f 2 = f in x -------------m+1
Register PLL1CONF
15
Lockedi Div2Eni Div1Eni Bypassi PUi RESi
0 Mi(3:0) Ni(5:0)
fin
X
(1) (0)
1 (m + 1)
f1 2..15 MHz
(n + 1)
f2
(1) (1)
fout
1/2
X
(0)
1/2
X
(0)
Figure 3-8
DPLL Structure
The division factor determined by m must be chosen such that intermediate frequency f1 is in the range 2..15 MHz based on the input frequency at signal `SYSCLK'. The multiplication factor determined by n must be chosen such that intermediate frequency f2 is twice or four times the final value in case of DPLL1. Finally, one or two divisions by the two factors (f1,f2) may be enabled in case of DPLL1 to achieve the final clock frequency. When choosing the factors m and n, two conditions must be met: * n=1..24: f1 must be in a range of 5..15 MHz n=25..63: f1 must be in a range of 2..6 MHz * f2 must be in a range of 100 to 200 MHz
3.2.5.3
Programming Example
The following numbers are assumed for this example: * ABM-3G internal core clock: 52 MHz
Data Sheet 53 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description * Clock supply: 52 MHz at signal SYSCLK In this example, signal SYSCLKSEL must be connected to VSS to connect the internal core clock to the DPLL1 output. (Please refer to Figure 3-7) DPLL1 Programming A reasonable value for parameter M1 in register "PLL1CONF" on Page 287 is M1 = 12 which results in f1 = 52 MHz / (12 + 1) = 4 MHz. Now a possible value for parameter N1 is N1 = 25 which results in f2 = 4 MHz * (25 + 1) = 104 MHz. To achieve the 52 MHz core clock division factor 1 shall be enabled. Thus, for this example the value 3B19H must be programmed to register PLL1CONF. The conditions given above are met because f1=4 MHz is in the range of 2..6 MHz (n=25) and f2=104 MHz is between 100 and 200 MHz. Note: Multiple combinations of parameters are possible to achieve a 52 MHz clock in this example.
3.2.5.4
Initialization Phase
After power-on reset, the DPLL is in bypass mode which means that signal `SYSCLK' is directly feeding the internal core clock. After basic configuration of at least the DPLL configuration registers, the bypass can be disabled which will make a glitch-free adjustment of the internal clocks to the selected frequency.
3.2.6
Reset System
The ABM-3G provides three different reset sources, as shown in Figure 3-9. The hardware signal RESET affects the entire device. The self-clearing software reset bit `SWRES' in register "MODE1" on Page 312 also affects the entire device. Hardware reset as well as software reset bit `SWRES' completely initialize the device into power-on reset state.
Data Sheet
54
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
Test/ Clocks UTOPIA Interface (PHY Side)
SSRAM IF
ARC
SDRAM Interface (up) UTOPIA Interface (Backplane Side) Cell Handler upstream
Buffer Manager (BM) AAL5
Queue Scheduler (QS)
Cell Handler downstream BSCAN uP IF SDRAM Interface (dn)
ARC
RESET
bit 15
SWRES
Register `MODE 1'
Figure 3-9
Reset System Overview
Note: Initialization of external and internal RAM must be started by software via command bits `INITRAM' and `INITSDRAM' in register "MODE1" on Page 312 following the device reset.
3.3
System Integration
The ABM-3G has two operational modes: Bi-directional mode and Uni-directional mode. The directional terminology for the modes refers to the usage of the ABM-3G cores, not to the connections. The connections are bi-directional in all cases. In Bi-directional mode, one ABM-3G core is used exclusively for the cells of a connection in the upstream direction and the other core exclusively handles cells of the same connection in the downstream direction. In Uni-directional mode, only one core always will be used to handle the cells of a connection both in up- and downstream direction. The two basic
Data Sheet
55
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description applications for these modes are the switch port line card application and the miniswitch, respectively. On a typical switch port line card, both the upstream and downstream cell flow pass through the same ABM-3G device. One ABM-3G core is used for each direction as shown in Figure 3-10.
SSRAM interface UTOPIA upstream receive MASTER SDRAM interface ABM-3G Core upstream UTOPIA upstream transmit SLAVE
Common LCI Table UTOPIA downstr. transmit MASTER P interface UTOPIA downstr. receive SLAVE JTAG interface
ABM-3G Core downstream SDRAM interface
Figure 3-10 ABM-3G in Bi-directional Mode The ABM-3G assumes that all connections are set up bi-directionally with the same Local Connection Identifier (LCI) in both directions. In the Infineon ATM chip set environment, the LCI is provided by the PXB 4350 E ALP and contains VPI, VCI, and PHY information. If the ABM-3G is not used with the ALP, it can extract the LCI from VPI or VCI fields or generate the LCI by using the internal Address Reduction Circuit (ARC). In a mini-switch application, the total throughput at 51.84 MHz is 687 Mbit/s. Only the UTOPIA Receive and Transmit interfaces at the PHY-side are active. Both ABM-3G cores are selected from the multiplexer options shown in Figure 3-11. Each cell is forwarded to both ABM-3G cores and the LCI table entry for the connection determines which of the two cores accepts the cell. The other core ignores it. Thus, each cell is stored and queued in one of the two cores. The cell streams of both cores are multiplexed together at the output. In normal operation, the schedulers are programmed such that the sum of all output rates does not exceed the maximum rate supported by
Data Sheet
56
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description the UTOPIA transmit interface. However, bandwidth overbooking of the interface is also possible, resulting in backpressure towards the respective ABM-3G core.
SSRAM interface UTOPIA upstream receive MASTER SDRAM interface ABM-3G Core upstream UTOPIA upstream transmit SLAVE
Common LCI Table UTOPIA downstr. transmit MASTER P interface UTOPIA downstr. receive SLAVE JTAG interface
ABM-3G Core downstream SDRAM interface
Figure 3-11 ABM-3G in Uni-directional Mode Using both Cores If the resources of one core are sufficient, the downstream core can be deactivated (see Figure 3-12). This reduces power consumption and allows omission of the external downstream SDRAM. It also permits the SSRAM to be smaller (see below).
SSRAM interface UTOPIA upstream receive MASTER
SDRAM interface ABM-3G Core upstream UTOPIA upstream transmit SLAVE
Common LCI Table UTOPIA downstr. transmit MASTER P interface UTOPIA downstr. receive SLAVE JTAG interface
ABM-3G Core downstream SDRAM interface
Figure 3-12 ABM-3G in Uni-directional Mode Using one Core
Data Sheet
57
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
3.3.1
LCI Translation in Mini-Switch Configurations
In Uni-directional applications, the ABM-3G can be programmed to make a minimum header translation. This is necessary in a Mini-Switch configuration as both the forward and backward direction of a connection traverse the devices in the same direction. The OAM functions in the Infineon ALP (PXB 4350) or AOP (PXB 4340) devices need the same LCI for forward and backward direction of a connection. This is clarified by the example shown in Figure 3-13 in which a connection is set up from PHY1 to PHY2. VPI/VCI1 is the identifier on the transmission line where PHY1 is connected. The terminal sends ATM cells with this identifier and expects cells in the backward direction from PHY2 with the same identifier. The ALP in the upstream direction translates VPI/VCI1 into LCI1, the unique local identifier for this connection in the upstream direction. Similarly, for the backward connection from PHY2 to PHY1, the ALP receives ATM cells from PHY2 with the identifier VPI/VCI2 and translates them into LCI2.
ABM-3G Uni-directional mode)
VPI/VCI1 Cores LCI1 LCI1 LCI2
Phy 1 HT ALP PXB 4350
LCI2
AOP PXB 4340
LCI1 LCI1 LCI2
HT Phy 2
VPI/VCI2
LCI2
LCI= LCI+/-1
HT = Header Translation LCI = Local Connection Identifier
Figure 3-13 Connection Identifiers in Mini-Switch Configuration For minimum complexity, the header translation of the ABM-3G is done by inverting the Least Significant Bit (LSB) of the LCI. This measure divides the available LCI range into two parts: odd LCI values for forward connections and even LCI values for backward connections (or vice-versa). That is, it reduces the available number of connection identifiers to 8192, because two LCI values are used per connection. This is not a restriction in the case of arbitrary address reduction modes as, for example,
Data Sheet
58
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description when the ALP chip is used with the CAME chip (PXB 4360), as ATM connections are always set up bi-directionally with the same VPI/VCI in both directions of a link. Refer to Register 110 "MODE1" on Page 312 for the configuration of the bi-directional and uni-directional mode, the enabling of the LCI toggling, as well as the deactivation of the downstream core. Note: In case of fixed address reduction, as, for example, when using the ALP with the built-in Address Reduction Circuit (ARC), the usable LCI range may be seriously restricted, depending on the PHY configuration.
Data Sheet
59
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
3.4
Buffer Manager and Queue Scheduler Details
This section provides more detailed information about buffering (cell acceptance) and scheduling (cell emission) functions.
*
Queue Scheduler Unit Empty Cell Cycle
Common Real-Time Queue
Scheduler Block 0
Scheduler Block j Buffer Manager Unit R R DEMUX
Cell Acceptance Algorithm
discard
accept
W F Q
R R
Scheduler Block 127
Denotes an optional per Queue Rate Shaper (PCR limited leaky bucket ) Denotes an absolute per Scheduler Block Rate
Figure 3-14 Cell Acceptance and Scheduling
Data Sheet
60
SBS
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
3.4.1 3.4.1.1
Buffer Manager Functional Overview
The basic function of the Buffer Manager (BM) is to decide whether an arriving cell is granted access to the shared buffer or is discarded. This is done by running the Cell Acceptance Algorithm (CAA) (see Chapter 3.4.1.7). The buffer manager tables accessed by the CAA are summarized in Figure 3-15.
Local Connection Identifier Table 16384 entries LCI
Connection Specific Data (up / down)
Scheduler Block Occupancy Table 2 x 128 entries Queue Configuration Table 2 x 8192 entries SBID QID
Queue Specific Data Scheduler Specific Data
TCID
Traffic Class Table 2 x 16 entries
Queue / Traffic Class Specific Data
Global Buffer Data
Cell Acceptance Algorithm
Figure 3-15 Buffer Manager Tables More generally, the buffer manager allocates the buffer resources needed to fulfill the specific service guarantees of individual connections. In a first step when receiving a cell, the Local Connection Identifier (LCI) that was previously assigned by the Header Translation (see Figure 3-13), is mapped to a corresponding Queue Identifier (QID). The QID represents the logical queue in which the cell will be stored upon acceptance and serves as an index for subsequent table lookups. In particular, the Scheduler Block and the Traffic Class of the received cell is identified with the Scheduler Block Identifier (SBID) and the Traffic Class Identifier (TCID) respectively. With any incoming cell, the Cell Acceptance Algorithm (CAA) can access the current buffer status information containing counters, thresholds and flags. Based on this data, the cell is either discarded or accepted. The respective counters are updated appropriately.
Data Sheet
61
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description Under normal operation conditions, once a cell is accepted by the CAA, it will be emitted at a time. The only reason for cell discard after cell acceptance is queue disabling. The cell itself is stored in the external cell store RAM. The logical queue is a linked list of pointers to the cell store RAM providing a FIFO ordering.
3.4.1.2
Logical Buffer Views
The ABM-3G Cell Buffer is structured by the Buffer Manager into the following major logical views: * * * * Global Buffer, Logical Queues, Scheduler Blocks, Traffic Classes.
Each view is characterized by attributes, state variables (e.g. occupancy counters), and programmable thresholds.
3.4.1.2.1 Global Buffer
A total amount of 262,140 cells can be stored per direction in the global cell buffer. Depending on the particular threshold configuration, global buffer space can be exclusively reserved or shared among different logical queues, scheduler blocks or traffic classes and the individual connections assigned to them.
3.4.1.2.2 Logical Queues
The concept of logical queues is implemented to provide isolation between connections or groups of connections sharing the global buffer. Strict per VC queueing is achieved by exclusively assigning connections to logical queues. However, it is also possible to assign more than one connection to a particular logical queue. A total of 8192 logical queues is provided per direction, with QIDs ranging from 0 to 8191. QID 0 is reserved for the common real-time (CRT) bypass queue. It may be used for realtime traffic in case of an unstructured ABM-3G output, as e.g. in input buffered switches and also for cascading multiple ABM-3Gs. The common real-time bypass is programmed as a rate limited queue. Section 3.4.2.1 provides scheduling related details.
3.4.1.2.3 Scheduler Blocks
From a buffer manager perspective, Scheduler Blocks (SB) can be conceived as a grouping of logical queues sharing the bandwidth provided by the configured SB rate. Each logical queue, except the common real-time (CRT) bypass (QID=0), is unambiguously assigned to a scheduler block. A total of 128 Scheduler Blocks is provided per direction.
Data Sheet 62 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description Scheduler Blocks are usually assigned to ports, logical channels, or limited terminated VPCs, providing the necessary rate adaptation. Section 3.4.3 provides the details. SB occupancy thresholds are provided for buffer protection in case of SB overload.
3.4.1.2.4 Traffic Classes
The concept of traffic classes is introduced to provide a logical grouping of queues with common properties, defined by a set of parameters. Each logical queue is unambiguously assigned to a traffic class and inherits the thresholds and flags defined therein. The Buffer Manager supports up to 16 distinct parameter sets for traffic classes in the Traffic Class Table (TCT). Each parameter set includes thresholds and flags as listed in Chapter 3.4.1.3. Figure 3-16 shows the independent assignment connections to queues and of queues to traffic classes and schedulers.
S c h e d u le r B lo c k 0
RR
WFQ
RR
S c h e d u le r B lo c k 1 2 7
T r a f fic c la s s 0
T ra ffic c la s s 1
T r a ff ic c la s s 1 5
V ir tu a l C o n n e c tio n to Q u e u e M a p p in g Q u e u e to S c h e d u le r M a p p in g Q u e u e to T r a ffic C la s s M a p p in g
Figure 3-16 Queue Assignment to Traffic Classes and Scheduler Blocks Traffic classes are the principal buffer management concept for Quality of Service (QoS) differentiation. They are not pre-defined or fixed to the standard ATM service categories. This allows for configuration of generic or new services (e.g. DiffServ Per Hop Behaviors (PHB) as defined by the IETF). Along with the queue scheduler concept of scheduler blocks (see Section 3.4.2.2), a wide range of QoS objectives can be met.
Data Sheet
63
RR
WFQ
RR
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
3.4.1.3
Threshold Classification
The different threshold types are listed in Table 3-17. In this section, each classification includes a short description.
3.4.1.3.1 Discard Thresholds
Discard thresholds are used by the Cell Acceptance Algorithm (see Chapter 3.4.1.7). The CAA is invoked every time a cell arrives and calculates a truth value from individual discard conditions. A discard condition is an expression involving thresholds, counters, flags, parameters, and state variables that renders a truth value as result. Several basic discard conditions can be combined to implement more advanced discard mechanisms (see Chapter 3.4.1.6). Basic Discard Conditions The simplest discard condition is the comparison of an occupancy counter with a threshold. A common classification of discard conditions includes: * Maximum A discard condition is classified as Maximum Fill if it is independent of the CLP transparency flag or if the CLP transparency flag is set to 1. * CLP1 A discard condition is classified as CLP1 if it is dependent on the setting of the CLP transparency flag to 0. * Packet A discard condition refers to a packet if it is dependent on the setting of EPDen = 1 or PPDen = 1. A particular threshold can participate in several discard conditions. In the ABM-3G, it is quite common to use a threshold in both maximum fill and packet discard conditions. Refer to Table 3-17. Discard Control Parameters Besides the simple comparison of a threshold value to a counter, several flags and variables are combined to provide more complex discard conditions. * CLP1DIS CLP1 thresholds are only enabled if the number of CLP1 cells in the SB, counted by SBOccLP is greater or equal to CLP1DIS. To enable CLP1 thresholds unconditionally, this threshold must be set to 0 in Register 19 "CLP1DIS" on Page 180. * MinBG This queue-specific threshold disables discard when the QueueLength counter is lower than MinBG. The description of the minimum buffer guarantee in Section 3.4.1.6.4 provides the details.
Data Sheet 64 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description * DH Delta Hysteresis is a traffic class specific factor applied to all maximum thresholds. The description of the hysteresis mechanism in Section 3.4.1.6.5 provides the details.
3.4.1.3.2 Backpressure Thresholds
* UTOPIA Backpressure Thresholds These thresholds (four in upstream and four in downstream direction) are global thresholds with respect to the cell buffer fill level and result in backpressure of specific port groups of the respective UTOPIA receive interface.
3.4.1.4
Counter Classification
The ABM-3G Buffer Manager contains the following counter types * Occupancy Counters These counters reflect the current buffer state and are basic elements in discard, congestion indication and backpressure mechanisms. * Statistics Counters These counters are used for measurements and statistics. Refer also to Chapter 3.4.1.8.
3.4.1.5
Threshold and Occupancy Counter Overview
Table 3-17 summarizes thresholds and occupancy counters used by the Cell Acceptance Algorithm. The thresholds are grouped by logical buffer view. For each arriving cell, all conditions in this table are checked. Several thresholds may be exceeded at the same time. Therefore, the table is not a truth table.
Data Sheet
65
2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description
Table 3-17
Logical Buffer View
Threshold and Counter Table
Threshold
Granularity
Location
GFRen
EPDen
PPDen
CLPT x x x x x x 0 0 0 x x x x 0 x x x 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 x x x x
CRT Queue
Enabling Flags
LCI Table DH
Related Occupancy Counter
Threshold Type
TCT3
Reg 16
BufMax
BufferOcc
Maximum PPD
4x 4x 1024 x 1024 x 1024 1 1024 1 1024 0 1024 0 1024 1 4x 4x 4x 4x
x 1 x 1 x x x 1 x x x x x x 1 x x x 1 x x x 1 x x
x x x x 0 1 x x x x x x x x x 0 1 x x x x x x 0 1
n n y n n n n n n n n n n y n n n n n n n y n n n
x 0/1 0/1 0/1 0/1 0/1 1 1 1 x x x x 0/1 0/1 0/1 0/1 1 1 1 1 0/1 0/1 0/1 0/1
TCT0
BufMaxNg
BufferOccNg
Maximum PPD 1)
TCT0
BufEPDNg
BufferOccNg
EPD GFR
Global Buffer
TCT1
BufCiCLP1
BufferOccNg
CLP1 PPD EPD
Reg 21 Reg 22 Reg 23 Reg 24 TCT3
UBTH0 UBTH1 UBTH2 UBTH3 SBMax
BufferOccNg
UTOPIA backpressure
SBOccNg
Maximum PPD
1024 0 1024 0 1024 1 1024 1 64 0 64 0 64 1 64 x 1024 0 1024 0 1024 1 1024 1
Scheduler Block
EPD GFR
TCT2
SBCiCLP1
SBOccNg
CLP1 PPD EPD
Reg 19
CLP1DIS TrafClassMax
SBOccLP TrafClassOccNg
Reservation Maximum PPD EPD GFR
Data Sheet
Traffic Class
TCT3
66
2001-12-17
CLP
Affected Cells
ABM-3G PXF 4333 V1.1
Functional Description Table 3-17
Logical Buffer View
Threshold and Counter Table
Threshold
Granularity
Location
GFRen
EPDen
PPDen
CLPT x x x x x x 0 x 1 x x x x x x x x x x x
CRT Queue
Enabling Flags
LCI Table DH
Related Occupancy Counter
Threshold Type
TCT3
Fixed
QueueLimit (16383) QueueMax
QueueLength
Maximum PPD
1x 1x 64 0 64 0 64 1 64 1 40 40 41 1, 8 x
x 1 x 1 x x x 1 x x
x x x x x 1 x x x x
n n y n n n n n n n
0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 0/1
TCT1
QueueLength
Maximum PPD
Queue
EPD GFR
TCT0
QueueCiCLP1
QueueLength
CLP1 PPD EPD
QCT2
1)
MinBG
QueueLength
Reservation
Not a true PPD threshold because the last cell of the packet is also discarded when BufMaxNg is exceeded.
Note: The flags in columns "TCT3 enabling flags" indicate the traffic class settings required to make the threshold effective during cell acceptance algorithm for a cell (connection) determined to belong to that traffic class. An `x' means don't care, i.e. the flag has no effect on the threshold. The same applies to flag "CLPT" which is a connection specific setting in the LCI table. The column "affected cells" indicates whether the threshold affects CLP0, CLP1 or all cells. Note: The thresholds and counters shown above are available in both the upstream and the downstream ABM-3G core. In case of registers, the variable name is prefixed with U for upstream and D for downstream in the register tables of Chapter 7.
3.4.1.6
Discard Mechanisms and Buffer Reservation
Each arriving cell is classified by determination of its QID, SBID, and TCID. The discard mechanisms available in the ABM-3G Buffer Manager are based on occupancy counters and the programmable thresholds described in Chapter 3.4.1.3 and Chapter 3.4.1.4.
3.4.1.6.1 Maximum Fill Discard
A maximum fill discard occurs if the cell counter exceeds the related maximum fill threshold at cell arrival.
Data Sheet 67 2001-12-17
CLP
Affected Cells
ABM-3G PXF 4333 V1.1
Functional Description The following maximum fill thresholds are available: BufMax, and QueueLimit are determined by physical limits. BufMaxNg, SBMax, TrafClassMax, QueueMax are configured per traffic class.
3.4.1.6.2 Selective CLP1 Discard
Selective discard is based on the CLP marking found in the arriving cells and is enabled by the CLP transparency flag (CLPT) stored per connection in the LCI table. In cell discard mode, the mechanism triggers tail drop for CLP=1 cells only. In this mode, the mechanism is used to limit the buffer space provided for the non-guaranteed part of VBR.2/.3 traffic. In packet discard mode, the mechanism triggers EPD for CLP=1 frames only. According to the GFR conformance definition, a CLP1 frame is assumed when the first cell of the frame is a CLP1 cell. In this mode, the mechanism is used mainly for the GFR service. The following discard thresholds are available to control selective CLP1 discard: BufCiCLP1, SBCiCLP1, QueueCiCLP1. Note: There is no selective CLP1 discard threshold available for the traffic class view.
3.4.1.6.3 Packet Discard
Packet discard mechanisms rely on the AAL5 End Of Packet (EOP) indication in the PTI field of the cell header. The ABM-3G implements two packet discard mechanisms: * Early Packet Discard (EPD) * Partial Packet Discard (PPD). Packet discard can be enabled individually per traffic class by setting the flags EPDen and PPDen in the TCT respectively. The dynamic status of an ongoing packet discard is stored per connection in the fields LastCellOfPacket, DiscardPacket and DiscardRestOfPacket in the LCI table. Both mechanisms are provided to avoid or reduce the volume in the transmission of corrupted packets and therefore improve utilization of buffer and bandwidth resources. Early Packet Discard (EPD) The Early Packet Discard (EPD) mechanism drops all cells of a packet if it decides to drop the first cell of that packet. In packet discard mode, if at cell arrival the related cell counter exceeds this threshold, and the flag LastCellOfPacket is enabled in the LCI table, indicating that the arriving cell is the first cell of a packet, then the cell is discarded and the flag DiscardPacket is enabled in the LCI table. All subsequently arriving cells of the packet are discarded without taking into consideration the cell counter. EPD may only be applied to non real-time connections. The mechanism is enabled by the software configurable flag EPDen, specified per traffic class in the TCT.
Data Sheet 68 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description The Buffer Manager attempts not to corrupt a packet, once it has accepted the first cell. This means that for EPDen=1, the maximum thresholds TrafClassMax, SBMax and QueueMax are disabled for the rest of the packet. Only the thresholds BufMax, BufMaxNg and QueueLimit can corrupt an accepted packet. Partial Packet Discard (PPD) Under the rare circumstances described at the end of the previous section, it may happen that a cell is discarded from within a packet although the EPD algorithm has accepted it. In this case it is meaningful to discard also all following cells of the packet. However, the last cell of a partially discarded packet should be buffered if possible, since the reassemble mechanism at the receiver is triggered by the last cells of user data packets. This mechanism is referred to as Partial Packet Discard (PPD). In packet discard mode, if at cell arrival the related cell counter exceeds this threshold, and the exceeding cell is not an end of packet or an OAM cell, then the cell is discarded and the flag DiscardRestOfPacket is enabled in the LCI table. All subsequently arriving cells of the packet, excluding the last cell of the packet, are discarded without taking into consideration the cell counter. PPD may only be applied to non real-time connections. The mechanism is enabled by the software configurable flag PPDen, specified per traffic class in the TCT. Note: EPD/PPD functionality is offered by the ABM-3G on a per VC basis. Hence, these functions can be supported also for connections sharing a queue. Note: Cell discarding due to EPD and PPD does not apply to non-user cells, e.g. an OAM cell within a packet is not discarded. GFR Packet Discard The EPD mechanism in combination with the flag GFRen is used to support the GFR service. GFR packet discard works only in conjunction with EPDen = 1 and discards only a well defined subset of the packets normally eligible for EPD. In particular, when EPDen = 1 and GFRen = 1, a packet is discarded only if: [(BufEPDNg or SBMax or TrafClassMax) and QueueMax] or any of the EPD CLP1 thresholds is exceeded. GFRen and PPDen are independent. GFRen has no influence on PPD and PPDen has no influence on GFR. GFRen has no influence on the discard of CLP=1 frames. Therefore there is no difference between EPD and GFR packet discard regarding CLP=1 frames.
3.4.1.6.4 Minimum Buffer Reservation
A minimum buffer reservation is provided on a per queue basis by setting parameter MinBG. As long as the queue length has not reached this value, an incoming cell can be
Data Sheet 69 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description stored without further checks, except the queue threshold checks. When the MinBG limit is exceeded, the Cell Acceptance Algorithm checks if buffer space is available in the non guaranteed buffer space.
BufMax
Reserved queue 1 Reserved queue 2 Queue 1 Reserved queue 3 Queue 2
QueueMax MinBG QueueLength
BufMaxNg BufEPD
BufferOccNg
Queue 3 Part of Buffer shared by all queues / connections
Shared buffer QueueLimit Reserved buffer
Figure 3-18 Buffer Management with per Queue Minimum Buffer Reservation For all traffic classes, the threshold BufMaxNg must be adjusted appropriately, such that, if LQ is the set of logical queues allocated so far, then: BufMax - BufMaxNg
i LQ
a
MinBG i
Although the ABM-3G in principle has the knowledge of all programmed guaranteed minimum queue sizes, it does not perform the summation for complexity reasons. Refer to Register 39 "QCT2" on Page 217 for the programming of minimum buffer reservation thresholds. If the condition in the formula above is not fulfilled, then error condition BCFGE occurs and is signalled in Register 101 "ISRU" on Page 297 or Register 102 "ISRD" on Page 300 respectively.
3.4.1.6.5 Hysteresis for Maximum Thresholds
Hysteresis is an optional feature for the maximum thresholds BufMaxNg, SBMax, TrafClassMax, and QueueMax in cell discard mode. Hysteresis means that cell discard starts when any of the maximum thresholds mentioned above (referred to as TH for convenience) is exceeded and continues until the level falls below a threshold TL that is considerably lower than TH.
Data Sheet 70 2001-12-17
ABM-3G PXF 4333 V1.1
Functional Description A hysteresis control parameter DHi is provided per traffic class i. It is used to calculate the low threshold TLi from a given high threshold THi according to: TL i = TH i - ( TH i [ DH i + 1 ] ) , with DHi ranging from 1 to 7. DHi=0 disables the feature. "DH" on Page 207 provides the programming details. An example for the hysteresis mechanism is shown in Figure 3-19 below. When TH is exceeded, a connection specific discard flag is set which is cleared again when the buffer fill falls below TL. This flag is used by the cell acceptance algorithm to differentiate between accept state and discard state.
B uffe r_size
THi TLi
tim e b uffer falls b elow T Li ce lls of traffic class i a re acce pted = > em ptyin g rate sinks, cle ar disca rd flag b uffer falls b elow T H i ce lls of traffic class i a re still dis carde d som e con nectio ns red uce ra te = > buffe r fill falls T H i is re ach ed, c ells of tra ffic class i a re d isca rd ed = > C e ll acce ptan ce rate is redu ced , s et d is card flag C ell a ccep tanc e rate is h ig he r than cell em ission ra te
Figure 3-19 Buffer Threshold with Hysteresis Hysteresis is not used with packet discard and CLP1 discard thresholds. Hysteresis avoids oscillation effects when the buffer fill is just stable at a certain value and this value just coincides with a certain threshold. A stable buffer fill occurs when input and output flow of the buffer are equal. However, due to cell clumping effects the fill value will vary with a cell jitter in the range 10..100 cells. The hysteresis threshold difference should be larger than the jitter.
3.4.1.7
Cell Acceptance Algorithm
The following pseudo-code provides the cell acceptance algorithm of the ABM-3G based on the parameter set listed in Chapter 3.4.1.3.
Data Sheet
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Functional Description
3.4.1.7.1 Discard Conditions
/***** Basic Max/EPD ExceedMaxBuffer = ExceedMaxGlobal = ExceedEpdGlobal = ExceedMaxSB = ExceedMaxTrafClass = ExceedMaxQueueLimit= ExceedMaxQueue = conditions **********************************/ (BufferOcc = BufMax) (BufferOccNg >= BufMaxNg) (BufferOccNg >= BufEPDNg) (SBOccNg >= SBMax) AND (QID != 0) (TrafClassOccNg >= TrafClassMax) (QueueLength = QueueLimit) (QueueLength >= QueueMax)
/***** Basic CLP1 conditions *************************************/ ActiveCLP1 = (CLP=1) AND (CLPT = FALSE) ExceedCLP1Global = ExceedCLP1SB = ExceedCLP1Queue = (BufferOccNg >= BufCiCLP1) AND ActiveCLP1 (SBOccNg >= SBCiCLP1) AND (QID != 0) AND ActiveCLP1 (QueueLength >= QueueCiCLP1) AND ActiveCLP1
/***** Basic reservation conditions ******************************/ ExceedMinBG = (QueueLength >= MinBG) ExceedCLP1DIS = (SBOccLP >= CLP1DIS) OR (QID = 0) /***** Derived conditions ****************************************/ ExceedMaxNg = ExceedMinBG AND {[ (EPDen = FALSE) AND ( ExceedMaxTrafClass OR ExceedMaxSB OR ExceedMaxQueue ) ] OR ExceedMaxGlobal } ExceedEpd = ExceedMinBG AND [ ExceedEpdGlobal OR ExceedMaxTrafClass OR ExceedMaxSB ] ExceedCLP1DIS AND {[ ExceedMinBG AND (ExceedCLP1Global OR ExceedCLP1SB) ] OR ExceedCLP1Queue } ExceedEpdCLP1 AND (EPDen = FALSE)
ExceedEpdCLP1 =
ExceedCLP1 =
3.4.1.7.2 EPD Algorithm
Based on the variables set by the EPD support parts of the threshold exceed algorithm and queue specific variables, the EPD algorithm decides upon the acceptance of a packet.
Data Sheet 72 2001-12-17
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Functional Description
IF THEN
ELSE IF THEN ELSE
LastCellOfPacket AND UserToUserCell IF [(ExceedEpd OR ExceedMaxQueue) AND (GFRen = FALSE)] OR (ExceedEpd AND ExceedMaxQueue) OR ExceedEpdCLP1 THEN DiscardPacket = TRUE ELSE DiscardPacket = FALSE Do nothing EPDen AND UserToUserCell AND DiscardPacket CellAcceptedByEPD = FALSE CellAcceptedByEPD = TRUE UserToUserCell AND EndOfPacket
LastCellOfPacket =
3.4.1.7.3 PPD Algorithm
If the PPD algorithm is applied, the last cell of a corrupted packet should be accepted.
IF THEN IF THEN ELSE PPDen AND UserToUserCell AND EndOfPacket DiscardRestOfPacket = FALSE PPDen AND UserToUserCell AND DiscardRestOfPacket CellAcceptedByPPD = FALSE CellAcceptedByPPD = TRUE
3.4.1.7.4 Hysteresis Algorithm
For any threshold TH:Delta(TH) = TH - TH/2**[DH + 1] with DH in 1..7 FillBelowHyst = (ExceedMinBG = FALSE) OR (DH = 0) OR [ (BufferOccNg < Delta(BufMaxNg)) AND ((SBOccNg < Delta(SBMax)) OR (QID = 0)) AND (TrafClassOccNg < Delta(TrafClassMax)) AND (QueueLength >= Delta(QueueMax)) ]
IF THEN IF THEN ELSE
UserToUserCell AND (PPDen = FALSE) AND FillBelowHyst DiscardRestOfPacket = FALSE UserToUserCell AND (PPDen = FALSE) AND DiscardRestOfPacket CellAcceptedByHyst = FALSE CellAcceptedByHyst = TRUE
Data Sheet
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Functional Description
3.4.1.7.5 Overall Cell Acceptance Algorithm
The overall decision whether an arriving cell is buffered is based on the results of the previous algorithms. The arriving cell can only be accepted if all algorithms would accept the cell and if buffer space is available. To obtain the overall decision whether a correctly received cell is finally buffered the following algorithm applies:
IF (ExceedMaxBuffer = FALSE) AND (ExceedMaxQueueLimit = FALSE) AND (ExceedMaxNg = FALSE) AND (ExceedCLP1 = FALSE) AND (CellAcceptedByEPD = TRUE) AND (CellAcceptedByPPD = TRUE) AND (CellAcceptedByHyst = TRUE) BufferIncomingCell DiscardIncomingCell IF PPDen AND UserToUserCell AND (EndOfPacket = FALSE) THEN DiscardRestOfPacket = TRUE IF PPDen = FALSE AND UserToUserCell AND ExceedMaxNg THEN DiscardRestOfPacket = TRUE
THEN ELSE
See Figure 4-9 for an example of threshold configuration.
3.4.1.8
Statistical Counters
In addition to the occupancy counters, which may also be used for statistical purposes, the ABM-3G device provides several dedicated counters for statistics purposes. These are summarized in Table 3-20:
*
Table 3-20
Location BM view
Statistical Counters Name
Width
Comment
Reg 17
UMAC/DMAC UMIC/DMIC
Buffer
16 Maximum buffer occupancy value since last readout 16 Minimum buffer occupancy value since last readout
Reg 18
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Functional Description Table 3-20
Location BM view
Statistical Counters (cont'd) Name
Width
Comment
TCT2 TCT3
AcceptedCells/ Packets LostPackets/CLP1Cells LostCellsTotal LostCellsBuffer LostCellsSB
32 Total transmitted cells or packets, selectable by flag SCNT 16 EPD discards or CLP1 discards 32 Total cell discards 4 Global buffer overflow cell discards 4 Scheduler block overflow discards 18 Scheduler block CLP1 cell discards
Traffic Class SB
TCT0 TCT2 TCT3 TCT1 TCT1
SBOC0 SBOccLPd SBOC1
Data Sheet
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Functional Description
3.4.2 3.4.2.1
Queue Scheduler Functional Overview
The basic function of the hierarchical Queue Scheduler (QS) is to properly allocate cell transmission slots to scheduler blocks and within those to queues, enabling them to send buffered cells. Thereby, the QS allocates the bandwidth resources needed to fulfill the specific service guarantees of individual connections. Internally, the QS functions are implemented by two basic building blocks: 128 identical scheduler blocks (SB) and a subsequent round robin scheduler (SBS) as depicted in Figure 3-21. In addition to these, a prioritized empty cell generator queue (for SDRAM refresh) and a Common Real-Time (CRT) queue which also has priority over the SBS, are provided. These two queues are assumed to be rate limited. Section 4.2.2.4 and Section 4.2.2.3 respectively provide the details on the programming of these queues.
*
Empty Cell Cycles Common RT Queue
SB0
R R
W F Q
SBS UTOPIA
Buffer Manager
R R
SB127
R R
W F Q
R R
Figure 3-21 Functional Structure of the Hierarchical Queue Scheduler In summary, the Queue Scheduler calculates a QID for each cell emission opportunity.
Data Sheet
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Functional Description
3.4.2.2
Scheduler Block
Each Scheduler Block (SB) is a cascade of two scheduling levels, a combination of Weighted Fair Queueing (WFQ) and Round Robin (RR) schedulers in the first stage, followed by a priority scheduler in the second stage as shown in Figure 3-22. An arbitrary number of queues from a maximum of 8191 can be assigned to each scheduler input at stage 1. (Queue 0 is reserved for the common real-time bypass).
Scheduler #j
optional PCR or VBR Shaper
(e.g. CBR, rt-VBR)
Real-Time Traffic
R R
(1)
highest priority
W0
Non Real-Time, Guaranteed Rate Traffic
(e.g. nrt-VBR, ABR, GFR, UBR+)
W1
W F Q
configured output rate
(2)
Wn
Non Real-Time, Best Effort Traffic
(e.g. UBR)
R R
(3)
lowest priority
Logical Queues
Multiplexers
Wi: WFQ Weight Factor
Figure 3-22 Scheduler Block Structure Scheduler Blocks are the principal queue scheduler concept for QoS differentiation. Together with the buffer manager concept of traffic classes, various QoS objectives can be met.
3.4.2.2.1 Priority Scheduler
The priority scheduler implemented in the scheduler block of the ABM-3G has three priority levels. As long as there are buffered cells destined to pass at priority 1, only these cells are served. Otherwise, buffered cells destined to pass at priority 2 are served. Only when there are neither priority 1 nor priority 2 cells buffered, then cells from priority 3 are allowed to pass. As a result the available bandwidth for priority 1 traffic is the total output bandwidth. The available bandwidth for priority 2 and priority 3 traffic is the leftover bandwidth from the next higher priority level respectively. Chapter 4.2.2.7 provides the details on the mapping of queues to the 3 priority levels.
Data Sheet 77 2001-12-17
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Functional Description
3.4.2.2.2 Round Robin Scheduler
The round robin scheduler keeps all of its input queues, which have cells to send in a FIFO structured list. The queue at the head of the list is allowed to send one cell and is then rescheduled at the end of the list. Thereby, the available bandwidth is divided equally among those queues which have cells to send.
3.4.2.2.3 Weighted Fair Queueing Scheduler
Rate guarantees for non real-time connections are achieved with the WFQ scheduler. The WFQ scheduler has an arbitrary number of input queues with a weight factor assigned to each of them. The absolute values of the weights are irrelevant, only the relative values count. See Chapter 4.2.2.7 for a discussion on appropriate selection of weight factors. The WFQ scheduler has the following important properties: * It is work conserving, i.e. the available bandwidth is always used completely as long as any of the attached queues has cells to send. * It provides a fair distribution of the available bandwidth in proportion to the assigned weights under any load condition. * It guarantees minimum rates to queues as long as the sum of the configured minimum rates fits into the available bandwidth. The properties above make the WFQ scheduler particularly useful for bursty connections with start/stop behavior. The WFQ scheduler automatically deals with the varying load situations and always distributes the bandwidth according to the weight factors.
Arrival Rate Priority Multiplexer Rate Round Robin WFQ
Figure 3-23 Behavior of Different Scheduler Types
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Functional Description For a given arrival rate Figure 3-23 shows the repartition of the output rate. The priority scheduler simply cuts off the low priority traffic assumed in the white bar. The RR scheduler iteratively divides the output rate into equal shares among the active inputs. The WFQ scheduler divides the output rate in proportion to the assigned weights assumed to be proportional to the respective arrival rates.
3.4.2.3
Quality of Service Support
In the context of ATM service categories, it is useful to introduce the concept of guaranteed rate. This is the rate which the network must guarantee to the user in order to fulfill the QoS demands. Table 3-24 Guaranteed Rates for each ATM Service Category ATM Service Category CBR rt-VBR Guaranteed Rate PCR SCR...PCR Guaranteed rate is calculated with "effective bandwidth formulas" assuming small buffers and taking into account statistical multiplexing gain. Guaranteed rate is delivered in complete uncorrupted AAL5 frames. Guaranteed rate is always > 0 with queue connected to the WFQ scheduler, can be 0 for arbitrary long times in low priority RR scheduler. Comment
nrt-VBR GFR UBR+ UBR
SCR MCR MCR none
Mapping of connections to stage 1 schedulers depends on the ATM service category of the connection (also shown in Figure 3-22) as follows: - Priority 1 RR: - Priority 2 WFQ: - Priority 3 RR: real-time connections (CBR, rt-VBR). non real-time connections with guaranteed rate (nrt-VBR, GFR, UBR+) best effort connections UBR
An example of a scheduler with one priority 1 real-time queue (Queue 1) and nine priority 2 non-real-time queues (Queue 2 through Queue 10) is shown in Figure 3-25. Queue 1 is shared by a number of connections with different bit rates.
Data Sheet
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Functional Description
9 7
Band width n ot reserved 10 9 8 7
10 9 8 7
6 6
6
scheduler output rate
5 4 3 2
1
1
1
real-time traffic
connection setup with guaranteed cell rates
not reserved bandwidth distributed
unused bandwidth distributed
Figure 3-25 Scheduler Behavior Example The three columns in Figure 3-25 describe different conditions: The left column shows the scheduler load as seen from Connection Acceptance Control (CAC). New connections are accepted as long as their guaranteed rates fit the spare bandwidth of the scheduler. The center column shows the case in which all Queues 2..10 are filled; that is, all non-real-time connections are sending data. The total non-real-time bandwidth, including the spare bandwidth, is then distributed to the 9 queues according to their weight. In this case, two weight factors are defined. Queue 6 has weight of 1, others have weight of 10. The right column shows the case of only three queues (6, 7 and 9) filled; all other connections are not sending data at this time. Again, the available bandwidth is fairly distributed among the queues, still conserving the 1:10 ratio defined by their weights. Notice that bandwidth of the real-time connections is not affected by bandwidth re-adjustments; but, remains constant over time under the assumption that real-time connections are constantly sending data. If, however, a real-time connection should not use its bandwidth, the bandwidth would be used immediately by the non-real-time connections. The behavior of the WFQ scheduler shown in Figure 3-25 for non-real-time connections has advantages for both the network operator and for the end user: * The available bandwidth is always used completely, resulting in optimum usage of transmission resources. * A user paying for a higher guaranteed rate also obtains higher throughput under all load conditions.
Data Sheet
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Functional Description
3.4.2.4
Traffic Shaping
Traffic shaping is a mechanism that alters the characteristics of a cell stream in order to make better use of network resources or to enforce conformance to the negotiated traffic contract at an interface. Conformance is defined operationally in terms of a Generic Cell Rate Algorithm GCRA(T,tau) which specifies the upper limits, in terms of a given tolerance tau, for cells arriving in excess with respect to a given reference cell rate (1/T). The ITU-T Recommendation I.371 [ 1 ] or the ATM Forum TM Specification 4.1 [ 2 ] provide the details. A situation that is particularly prone to produce non-conforming traffic is congestion in a network. Figure 3-26 shows the need for shapers at the output of a congested network for nrt-VBR traffic. An nrt-VBR cell stream originally shaped to conformance by the terminal (1) traverses Network A, which exhibits burst level congestion. At the output of Network A the cell stream is accumulated into a single large burst, which by far exceeds even the Peak Cell Rate (PCR) of the original connection (2). It is no longer conforming to the traffic contract and therefore would not pass through the subsequent policer. Hence, at the output of Network A, an SCR shaper is enabled, which regenerates a conforming cell stream to match a given burst tolerance BT (3). This cell stream is accepted by the policer and traverses Network B which exhibits cell level congestion only. As a result PCR and SCR vary slightly due to the cell clumping effect (4). This Cell Delay Variation (CDV) is reduced to match a given tolerance (CDVT) by the PCR shaper at the output of Network B (5).
Terminal Shaper Policer Network A Shaper Policer Network B Shaper Policer
burst level congestion rate
BT
cell level congestion
CDVT
PCR SCR
1
2
3
4
5
Figure 3-26 Shaping and Policing at Network Boundaries Note that the outcome of Network B has a very different shape when compared to the input to Network A and to the outcome of Network A. Nevertheless, due to the shapers implied, the traffic is conforming on both the User-Network interface (UNI) and the subsequent Network-Network Interfaces (NNI).
Data Sheet
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Functional Description The ABM-3G contains two basic shaping mechanisms, which can be activated per logical queue: PCR limitation and leaky bucket shaping. In particular it is possible to enable both mechanisms simultaneously on the same logical queue, a necessary feature to implement true VBR shaping as explained below.
3.4.2.4.1 PCR Limitation
For all logical queues a rate limitation can be enabled, which controls the peak cell rate (PCR) from this queue. In other words, cells from a PCR limited queue are always spaced by at least TP=1/PCR seconds. Cell clumping within the network is thereby eliminated. Traffic passing through a PCR limiter is conforming to any PCR traffic contract, since the tolerance of the PCR limiter is zero.
3.4.2.4.2 Leaky Bucket Shaping
A leaky bucket shaper controls a given sustainable cell rate (SCR) within the limits of a given Burst Tolerance (BT). The Burst Tolerance and the SCR determine the Maximum Burst Size (MBS) (in cells) that may be transmitted at an arbitrary PCR according to the following formula (refer to [ 2 ] ): MBS = BT 1 + -------------------------------1 1 ------------ - -----------SCR PCR [ cells ] (1)
Vice versa, when the MBS is received (via signalling), the corresponding BT can be calculated according to the following formula: 11BT = ( MBS - 1 ) ae ------------ - ------------ o e SCR PCRo [s] (2)
In the ABM-3G leaky bucket shaping can be enabled for up to 2048 PCR limited logical queues. In addition to the parameter TP = 1/PCR, the cell spacing for TS = 1/SCR and the burst tolerance tauS = BT must be specified. Figure 3-27 shows the outcome of the ABM-3G leaky bucket shaper under ideal conditions when loaded with a burst.
Data Sheet
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Functional Description
rate PCR PCR
rate
MBS SCR time SCR time
Input Burst
Figure 3-27 Ideal ABM-3G Shaper Output
Leaky Bucket Shaper Output
The implementation of the combined shaper guarantees sending the MBS as fast as possible without exceeding the PCR. If several cell streams are shaped simultaneously, it may happen that cells from different shapers would have to be sent out at the same cell slot. If N cell streams are shaped, in rare cases, a cell may have to wait up to N-1 cell cycles for transmission. This temporary loss of rate is compensated for by slightly stretching the burst in time. The additional CDV introduced to the PCR by this effect is monitored. With parameter CDVMax an upper limit on the CDV than can occur without notice is programmed. If this value is exceeded, an interrupt is generated. "UCDV/DCDV" on Page 239 provides the details. The difference between ideal and real shaper output is shown in Figure 3-28
rate PCR PCR
rate
Average rate PCR
MBS SCR time SCR
MBS
Average rate = SCR time
Ideal
Figure 3-28 Ideal and Real ABM-3G Shaper Output
Real
Data Sheet
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Functional Description Table 3-29 summarizes the parameters needed for combined PCR and SCR shaping. Table 3-29 Parameter Summary of VBR Shaping Parameters Derived from 1/PCR 1/SCR MBS or BT Stored in Table/ Register AVT:TP AVT:TS AVT:tauS AVT:Config UCDV/DCDV Range Min. Value *) *) 0 0 16 cell cycles Max Value
TP TS tauS VBR2.3 CDVMax
16 bit 16 bit 16 bit 1 bit 8 bit
65471 65471 64511 1 255 x 16 cell cycles
*) Refer to Table 4.2.2.5f for an explanation of shaper parameter ranges and granularities.
3.4.2.4.3 Shaping for VBR conformance
The standards define three conformance definitions for rt-VBR and nrt-VBR, referred to as VBR.1, VBR.2 and VBR.3. Table 3-30 explains the differences between the three VBR conformance definitions in terms of the relevant cell stream: index 0+1 denotes both CLP=0 and CLP=1 cells while index 0 denotes CLP=0 cells only. Table 3-30 VBR.1 VBR.2 VBR.3 VBR Conformance Definitions PCR Conformance GCRA(PCR 0+1, CDVT PCR) GCRA(PCR 0+1, CDVT PCR) GCRA(PCR 0+1, CDVT PCR) SCR Conformance GCRA(SCR0+1, BT) GCRA(SCR0, BT) GCRA(SCR0, BT), non conforming CLP=0 cells may be tagged (CLP set to 1)
Hence, from a shaping perspective, there is no difference between VBR.2 and VBR.3. As a consequence, the leaky bucket shaper in the ABM-3G is configurable on a per queue basis to shape either the CLP=0+1 cell stream (config parameter VBR2,3 = 0) or alternatively the CLP=0 cell stream only (config parameter VBR2,3 = 1). The PCR limiter always shapes the CLP=0+1 cell stream. By enabling a Leaky Bucket Shaper with the parameters TP=1/PCR, TS=1/SCR, tau = BT and VBR2,3 = (0|1), the ABM-3G can be used to produce conforming VBR traffic.
Data Sheet
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Functional Description Note that the PCR limiter does not make use of the tolerance CDVTPCR where transmission at higher rates than PCR would be possible. However, CDVTPCR is primarily intended to allow cell clumping and other networks artifacts, not to allow a higher rate. As mentioned earlier, this more rigid shaping does not violate PCR conformance.
3.4.2.4.4 Shaping for CBR conformance
In cases where simple PCR limitation is not sufficient for service categories that define a PCR conformance only, such as CBR, it is possible to use the leaky bucket shaper with parameters TS=1/PCR and tau=CDVTPCR. The parameter TP can be set to any suitable value to reflect higher allowed rates than PCR.
Data Sheet
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Functional Description
3.4.2.5
VC-Merge and Dummy Queue
Any queue can be configured (mutually exclusive) to participate in a VC-merge group or as a `dummy queue'. A detailed description of enabling/disabling those special queue functions is provided in the description of "Queue Configuration Table Transfer Registers QCT0..6" on Page 211.
3.4.2.5.1 VC-Merge
Several logical queues carrying AAL5 packets may be grouped together into one of a maximum of 128 merge groups. Functionally, a Packet Round-Robin (PRR) scheduler stage is inserted between the queues of the merge group and the first scheduling stage of the scheduler block. Whenever a complete packet is queued in a QID of a merge group, this QID is enabled to the PRR. The PRR schedules a QID to the SB until all cells of the current packet are transmitted. Then it switches to the next enabled QID. Hence, viewed from the Scheduler Block, a merge group appears like a single queue with the additional benefit that the output VC maintains AAL5 packet boundaries. See Figure 3-31.
VCx
Packet a
Merge Group QIDx
Active QIDx
Output with VC merge function Packet b Packet c Packet a VC
Packet b VCy QIDy
Output without VC merge function VCz ATM cell optional shaper Packet c QIDz Packet-RR SB Packets destroyed
Figure 3-31 VC Merge Scheduling Any queue can be configured to be member of one of the 128 merge groups in the QCT by setting 'RSall' = 0 in Register 38 "QCT1" on Page 214 and then setting 'MGconf/ DQsch' = 1 and 'MGID' to the desired merge group identifier in Register 39 "QCT2" on Page 217. If the queue is the first queue of the merge group, then its QID must be written into field 'Head_Pointer' in Register 51 "MGT2" on Page 234. Assigning a queue to a VC-merge group already enables the packet boundary aware scheduling of all queues within the same group.
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Functional Description Optionally, the ATM cell header may be overwritten with a new value programmed in the MGT by setting 'LCIOen' = 1 and 'LCI' to the desired value in Register 51 "MGT2" on Page 234. A queue is released from its VC-merge group by setting `QIDvalid' = 0 in Register 38 "QCT1" on Page 214. It is recommended to set the parameters of the individual queues in a merge group to equal values, reflecting the desired properties of the outgoing merged VC. In particular, the user must make sure that all queues of a merge group are assigned to the same SB. Also, for the optional shaping of a merged VC, the shaping parameters TP, TS, tauS and Config must be specified for each of the logical queues of the merge group and should all be equal to the intended shaping parameters of the outgoing merged VC. The VC-merge shaping mechanism works round robin on a per queue basis with the changing of the QID going on transparently behind the scene. Hence, viewed from the outgoing VC, there is no difference between a single queue VBR shaping and a merge queue VBR shaping. In particular, no cell slot is lost on the transition between queues.
3.4.2.5.2 Dummy Queue
A `dummy queue' (in contrast to a normal queue) is always scheduled by the queue scheduler according to its associated rates and parameters, even though it does not contain stored cells. Scheduling a dummy queue results in an 'empty cell cycle' (no cell is emitted during this cycle). Storing cells into a dummy queue is possible, but not recommended, since the cells are never emitted. Dummy queues can be used for bandwidth reservation e.g. for subsequent multicast operation or any other cell insert/multiplier process. A queue can be configured as a `dummy queue' by setting 'DQac = 1' and `RSall' = 1 in Register 38 "QCT1" on Page 214. This may only be done if 'MGconf/DQsch' = 0 in Register 39 "QCT2" on Page 217 and the queue is empty (QueueLength = 0).
Data Sheet
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2001-12-17
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Functional Description
3.4.3
Scheduler Block Usage
The ABM-3G allows arbitrary assignment of connections to queues and of queues to scheduler blocks. A scheduler block can be assigned to any UTOPIA PHY. Usage of a scheduler differs in switch input (upstream) or output (downstream). For the Mini-Switch application the upstream case does not exist. At a switch output, the scheduler blocks provide constant cell streams to fill the payloads of the PHYs. Either the entire cell stream of a PHY is provided or it is disassembled into several VPCs as shown in Figure 3-32. A VPC may contain both real-time and data connections. This is the case for a VPC which connects two corporate networks (virtual private networks), for example. The scheduler block concept has the advantage that data traffic is automatically adjusted after setup or teardown of a real-time connection. The output rate of a scheduler block in both applications is usually constant. The scheduler blocks always react to UTOPIA backpressure or can be controlled completely by backpressure instead of shaping. All scheduler blocks whose physical outputs are asserting backpressure hold on serving. Scheduler blocks serving time slots which are lost due to temporary backpressure are maintained and served later, if possible. Therefore, the rate with some CDV will be maintained. The maximum number of stored time slots which can be configured is equal to the maximum burst possible for that port or path.
Queue and Scheduler Block Assignment
Switch Fabric ABM-3G for Port 1
Virtual Paths, PHYs and Ports
PHY 1
SB
Port 1
SB
VPC 1 PHY n
SB
VPC m
Figure 3-32 Scheduler Block Usage at Switch Output At a switch input, each scheduler block is assigned to a switch output (Figure 3-33). A switch with n ports needs n2 scheduler blocks. The output rate of each scheduler block
Data Sheet 88 2001-12-17
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Functional Description is re-adjusted continuously to obtain maximum switch throughput without overloading the switch port output rate. This principle is called Preemptive Congestion Control, that is, congestion due to overload is avoided.
Ingress Port 1 (ABM-3G)
SB 1
Switch Fabric
Egress Port 1 R 1,1
Switch Fabric Egress Port Bottleneck 622 Mbps
SB n
R n,1
SB 1
R 1,n
Switch Fabric Egress Port Bottleneck 622 Mbps
SB n
R n,n
Egress Port n Ingress Port n (ABM-3G)
Switch Fabric Ingress Port Bottlenecks
R i,j Rate through Switch from
Fabric Ingress Port i to Fabric Egress Port j
Figure 3-33 Scheduler Block Usage at Switch Input There are two options for scheduler block rate adjustment: * After each connection setup or trade-in (static bandwidth allocation). * Backpressure controlled.
3.4.4
Scheduler Block Scheduler (SBS)
The SBS performs a weighted round robin scheduling among the active SBs. As long as the sum of the configured SB rates is below the service rate of the SBS, each SB receives bandwidth up to the configured rate, depending on the load in the SB. The SBS is said to be overbooked if the sum of the configured SB rates is above the service rate of the SBS. In this case, the SBS behaves like an RR scheduler for the overbooked SBs, which all receive an equal amount of bandwidth. The SBS supports up to 128 Scheduler Blocks per direction. In addition to this, a common real-time bypass queue (with fixed QID = 0) is supported.
Data Sheet
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2001-12-17
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Functional Description
3.4.5 3.4.5.1
Supervision Functions Cell Header Protection
To guarantee that the cell header is not corrupted by the external SDRAM, it is protected by an 8-bit interleaved parity octet. It extends over the 5-octet standard header including the UDF1 octet. The BIP-8 octet is calculated for all incoming cells and stored at the place of the UDF2 octet. When a cell is read out, the BIP-8 is calculated again and is compared with the stored BIP-8. In case of a mismatch, an 'BIP8ER' (Register 101: ISRU, Register 102: ISRD) interrupt is generated and the cell is discarded or not, depending on the configuration. cell header protection by BIP-8 can be disabled to achieve UDF2 transparency.
3.4.5.2
Cell Queue Supervision
The queueing of cells in the ABM-3G is implemented mostly by pointers. To detect pointer errors, the number of the queue in which the cell is stored is appended to the cell in the external cell storage SDRAM. When the cell is read out later, the selected queue number is compared to the QID stored with the cell. In case of a mismatch, a 'BUFER4' (Register 101: ISRU, Register 102: ISRD) interrupt is generated. See also "Upstream/ Downstream Cell Flow Test Registers" on Page 156.
3.4.5.3
Scan Unit
The basic function of the Scan Unit is to periodically refresh outdated variables and detect idle connections. The Scan Unit generates the (relative) cell clock Tnow needed by the VBR shaping mechanism and two (absolute) 1.25 ms and 10 ms clocks referred to as ms125count and ms10count. The Scan Unit accesses the complete AVT Context RAM periodically every 1.25ms. In a first step dword0 containing the Config(6:0) bits is read. These bits are interpreted and then in a second step the respective dwords are read which contain the time information. In case of time-outs the information is modified and written back.
Data Sheet
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Functional Description
SYSCLK 40 ..52 MHz
Divider /32
CellClk * 2**TstepC
Tnow 24 bit
Period 1.25ms Period 10ms
VBR
ms125count 8bit ms10count 8bit
Divider /256
Programmble Divider
Figure 3-34 SCAN Timer Generation The 40...60 MHz SYSCLK is divided by 32 to obtain a cell clock CellClk. The Tnow counter with 24-bit width increments by 2**TStepC every CellClk. The value of this counter is made available as relative time reference to other blocks. Parameter TStepC is set in Register 63 "USCONF/DSCONF" on Page 246. The absolute time bases are provided by dividing the CellClk first by 256 and then by a programmable divider of 7 bit (1...127). Timer ms125count is derived from bit 4 of the programmable divider. Timer ms10count is derived by from bit 7 of the programmable divider. The divider is programmed with the parameter SCANP found in register "ERCCONF0" on Page 286 depending on the SYSCLK value: Table 3-35 Timer Values for Clock Generation SCANP 49 63 period of ms10count [s] 0.010035 0.009956 delta [%] 0.35 0.44
Frequency [MHz] 40 51.84
Default value is SCANP=63, for the frequency of 51.84 MHz, which is easy to obtain as 1/3 of 155.52 MHz, the SDH/Sonet frequency. The following scan is performed:
Data Sheet
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Functional Description * For VBR Scan over all VBR QID Refresh TETvalid=Config[0], STvalid=Config[1] and TeV The Scan Unit can be disabled with flag SCAND found in register "ERCCONF0" on Page 286.
Data Sheet
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2001-12-17
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Functional Description
3.5 3.5.1
Internal Tables Table Overview
The ABM-3G provides a set of internal tables for configuration and runtime parameters. Figure 3-36 gives an overview of all (user accessible) tables and related control/transfer/ mask registers:
*
LCI Table MAR = 00d Mask Registers
TCT Table MAR = 01d
QCT Table MAR = 02d
SBOC Table MAR = 03d
MGT Table MAR = 07d
Common Mask Register Set: LCI0 LCI1 LCI2
MASK6
MASK5 MASK2 QCT0 QCT1 QCT2 QCT3 QCT4 QCT5 QCT6
MASK4 MASK1 SBOC0 SBOC1 SBOC2 SBOC3 SBOC4
MASK3 MASK0 MGT0 MGT1 MGT2
Data Transfer Registers
TCT0 TCT1 TCT2 TCT3
Common Table Access Control Registers: MAR WAR
Data Transfer Registers
ERCT1 ERCT0
UQPT1T1 UQPT1T0
UQPT2T3 UQPT2T2 UQPT2T1 UQPT2T0
DQPT1T1 DQPT1T0
DQPT2T3 DQPT2T2 DQPT2T1 DQPT2T0
USCTFT
DSCTFT
Mask Registers
ERCM1 ERCM0
UQPTM3 UQPTM2
UQPTM2 UQPTM0
DQPTM3 DQPTM2
DQPTM2 DQPTM0
USCTFM
DSCTFM
AVT Table MAR = 10d
QPT1 Table Upstream MAR = 16d
QPT2 Table Upstream MAR = 17d
QPT1 Table Downstr. MAR = 24d
QPT2 Table Downstr. MAR = 25d
SCTF Table Upstream MAR = 23d
SCTF Table Downstr. MAR = 31d
SCTI Table Upstream
SCTI Table Downstr.
no Mask USCTI
no Mask DSCTI
SCTI Table Access Control Registers: DSADR USADR
Figure 3-36 Table Access Overview
Data Sheet 93 2001-12-17
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Functional Description The tables are accessed by the microcontroller via control registers, data transfer registers and mask registers. While the control registers "MAR" on Page 307 and "WAR" on Page 309 are common to all tables (except SCTI tables), sets of mask registers are dedicated or shared among some tables. Data transfer registers are always dedicated to the specific table.
3.5.2
LCI: Local Connection Identifier Table
The basic function of the LCI table is assigning the connection (identified by the LCI) to one out of 8192 queues per direction. Single connections can be assigned to a dedicated queue (per VC queueing) or multiple connections might be assigned to the same queue. "LCI Table Transfer Registers" on Page 191 provides the details.
3.5.3
QCT: Queue Configuration Table
The basic function of the QCT table is to determine queue specific parameters and to assign the queue to dedicated resources (Traffic Class, Scheduler Block, Merge Group). "Queue Configuration Table Transfer Registers" on Page 211 provides the details.
3.5.4
QPT: Queue Parameter Table
The function of the QPT table is to configure the weight factor (in case a queue is assigned to the WFQ scheduler) and the peak cell rate value (in case the peak cell rate shaper is enabled). "Queue Parameter Table Transfer Registers" on Page 247 provides the details.
3.5.5
TCT: Traffic Class Table
The function of the TCT table is to configure the buffer management behavior of up to 16 traffic classes. "Traffic Class Table Transfer Registers" on Page 195 provides the details.
3.5.6
SBOC: Scheduler Block Occupancy Table
The function of the SBOC table (for 2*128 scheduler blocks) is to maintain the buffer filling levels associated with the dedicated scheduler. "Scheduler Block Occupancy Table Transfer Registers" on Page 223 provides the details.
3.5.7
SCT: Scheduler Configuration Table
The function of the SCT table (for 2*128 scheduler blocks) is to determine the integer part (SCTI) and fractional part (SCTF) of the scheduler block output rates as well as the UTOPIA port number the scheduler is assigned to.
Data Sheet 94 2001-12-17
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Functional Description "Scheduler Configuration Table Integer Transfer Registers" on Page 257 and "Scheduler Configuration Table Fractional Transfer Registers" on Page 267 provide the details.
3.5.8
MGT: Merge Group Table
The function of the MGT table (for 128 merge groups per direction) is to enable and specify the cell header overwrite function for the merge group output streams. "Merge Group Table Transfer Registers" on Page 230 provides the details.
3.5.9
AVT: VBR Configuration Table
The AVT table is the main context RAM of the VBR shaping sub-system.
3.5.9.1
AVT Context RAM Organization and Addressing
The AVT Context RAM addressing scheme imposes some restrictions to the choice of QID numbers for support of VBR shaping. The table is organized into 2 K sections of 4 double words (32-bit) each whereas each section corresponds to the respective QID number. Support of VBR shaping requires one section per connection, i.e. up to 2k-1 connections assigned to QID numbers (1, ..., 2047) can be supported for VBR shaping. QID 0 is reserved for the common real-time queue.
Data Sheet
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Functional Description
*
QID
31
0
RAM DWord Address: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QID 0
VBR Context Offset Address:
Reserved
1
DWord #0 DWord #1 DWord #2 DWord #3
2
3
8184 8185 8186 8187 8188 8189 8190 8191 31 0
2046
2047
Figure 3-37 AVT Context RAM Addressing Scheme The parameter utilization of each section depends on the mode selected for the particular queue (QID) in the Config field of the section. The mode specific parameter sets are described in subsequent chapters.
Data Sheet
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Functional Description
3.5.9.2
AVT Context RAM Section for VBR Shaping Support
In VBR shaping mode, one connection entry requires one AVT Context RAM section with a total of four double words. Since the AVT table is accessed from the external micro controller via a 16-bit transfer register, the VBR connection context appears as a 16-bit organized table with 8 entries as shown in Table 3-38: Table 3-38
15 14
AVT Context Table: VBR Shaping (Table Layout)
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 2a 3a 2b 3b 4 5 6 7
Config(6:0) TET(15:0) ST1(12:0) ST0(9:0) unused VDT(15:0) unused TS(15:0) TP(15:0)
TeV
TET(23:16) ST0(12:10) STf(5:0) VDT(18:16) Temit(12:0)
tauS(15:0)
Note: Entry 2/3 is used for 2 purposes: a) Internal Relog-Relog/Reschedule: two possible ST values for low and high priority cells b) Relog/Reschedule-Emit: VDT of next cell Table 3-39 Parameter Config(6:0) tauS(15:0) TP(15:0) TS(15:0) TET(23:0) VDT(18:0) AVT Context Table: VBR Shaping Parameter Description Initial Value configure configure configure configure don't care don't care Comment See Section 3.5.9.3 for mapping Delay tolerance parameter tau for SCR extension (15:10) and integer (9:0) part Rate parameter for peak rate limiter integer (15:6) and fractional (5:0) part Rate parameter for SCR-Leaky Bucket integer (15:6) and fractional (5:0) part Theoretical Emit Time for SCR Virtual departure time of cell extension (18:16), integer (15:6) and fractional (5:0) part
Data Sheet
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Functional Description Table 3-39 Parameter ST0(12:0) ST1(12:0) STf(5:0) TeV Temit(12:0) AVT Context Table: VBR Shaping Parameter Description (cont'd) Initial Value don't care don't care don't care 0 don't care Comment Scheduled departure Time for CLP=0 cell extension (12:10) and integer (9:0) part Scheduled departure Time for CLP=1 cell extension (12:10) and integer (9:0) part Scheduled departure Time common fractional part for CLP=0 and CLP=1 Temit valid Real Emit Time
Data Sheet
98
2001-12-17
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Functional Description
3.5.9.3
Common AVT CONFIG Field
The first word (WORD0) of each entry defines the entry type (inactive, VBR) with its respective submodes. The mapping of the 7 configuration bits Config(6:0) is summarized in Table 3-40. Table 3-40 Config field bit position Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Config(6:0) Bit Map absolute WORD bit position Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Function
enable reserved Core select VBR mode used internally used internally used internally
'1' VBR shaping enabled `0' `0': upstream core `1': downstream core `0': VBR1 `1': VBR2 and VBR3 CLP def. don't care STvalid def. 0 TETvalid def. 0
Data Sheet
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Operational Description
4
4.1
Operational Description
Basic Device Initialization
The following actions are recommended to be performed after reset to prepare the ABM-3G chip for operation: Basic settings * * * * Configure clocking system (DPLLs) Check register reset values Initialize SDRAM Reset internal tables (RAM)
ABM-3G diagnostic possibilities * Check all internal RAM and register values * Check external RAM Data path setting and initial queueing and scheduling initialization * Set MODE1 and MODE2 registers (Uni-directional Mode or Bi-directional Mode) * Configure UTOPIA Interfaces: modes, number of PHYs * Set global thresholds * Initialize traffic class tables * Set interrupt mask registers * Programming of Scheduler output rates * Programming of Empty Cell Rate generator * Programming of Common Real Time Queue rate * Assignment of Scheduler Blocks to PHYs at switch egress side * Assignment of Scheduler Blocks to switch outputs at ingress side Refer to the detailed register descriptions in Chapter 7 for a complete picture of the necessary initializations.
4.2
Basic Traffic Management Initialization
To set up a connection, the complete table structure must be established: LCI QID SBID and LCI QID TCID (see Figure 4-1). Additionally, bandwidth and buffer space reservations must be performed (see below). Depending on the traffic class, special functions must be enabled; for example: EPD/PPD for UBR.
Data Sheet
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Operational Description
16k common entry(Dn/Up) LCI Table
LCIsel
UpQID(13) Upflags(3) DnQID(13) Dnflags(3) ABMcore(1) CLPT(1)
2*128 entries SBOC Table SBOccNg(18) SBOccHP(18) SBOccLP(18) SBOccLPd(18)
2*8k entries QCT Table
Downstream Scheduler Block Upstream Scheduler Block 128 entries SCTI (Up) Table IntRate(14) Init(8) UtopiaPort(6) 128 entries SCTF (Up) Table FracRate(8)
DnQID
UpQID
MinBG(8) SBID(7) QIDvalid(1) RSall(1) DQac(1) QueueLength(14) TCID(4) MGconf/DQsch(1) MGID(7)
8k entries QPT1 (Up) Table
UpQID DnQID
flags(2) 8k entries QPT2 (Up) Table RateFactor(16) WFQfactor(14)
2*16 entries TCT Table
TCID
2k entries AVT (Up) Table 2*128 entries MGT Table MGHead(13) LCIoen(1) LCI(14) SbMax(8) TraffClassMax(8) GFRen(1) SCNT(1) PPDen(1) EPDen(1) DH(3) SbCiCLP1(12) QueueMax(8) BufCiCLP1(18) QueueCiCLP1(12) BufEPD(8) BufMax(8) Config(7) TP(16) TS(16) tauS(16)
Figure 4-1
Parameters for Connection Setup (bit field width indicated)
Data Sheet
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Operational Description Figure 4-1 refers to the following parameters: ABM-3G Transfer Register Parameter Description See page
CLPT LCI0 ABMcore
If set, the CLP bit of the cells is ignored. (not to be set for GFR; optional for UBR) Selects upstream or downstream ABM-3G Core in the Uni-directional Mode Points to the queue assigned to this connection in the downstream direction PPD(0), EPD(1), EOP(2) Points to the queue assigned to this connection in the upstream direction PPD(0), EPD(1), EOP(2) Status value (Read only) Selects the Scheduler Block Enables queue; if cleared, cells directed to this queue are discarded and interrupt QIDINV (see 7-297f.) occurs Selects the Traffic Class Enables the dummy queue function Status bit Minimum buffer guaranteed per queue Selects the VC-Merge Group the queue is assigned to Command bit to enable merge group assignment or dummy queue status indication
7-192
7-192
DnQID LCI1 Dnflags UpQID LCI2 Upflags QCT0 QueueLength SBID QIDvalid
7-193
7-193 7-194
7-194 7-214 7-214 7-214
TCID QCT1 RSall DQac MinBG MGID QCT2 MGconf/DQsch
7-214 7-214 7-214 7-217 7-217
7-217
Data Sheet
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Operational Description ABM-3G Transfer Register Parameter Description See page
BufMax
Defines maximum number of non-guaranteed cells allowed in the entire buffer for this traffic class Defines threshold for EPD/maximum 1) for this traffic class for the entire buffer Combined threshold for each queue for CLP=1 cell discard in case of CLPT=0 Defines threshold for each queue for this traffic class This 8-bit value determines a global cell filling level threshold with a granularity of 1024 cells that triggers early packet discard (EPD) for CLP=1 tagged frames used by GFR traffic class service (low watermark) This threshold determines a maximum number of low priority cells allowed to be stored per scheduler block with a granularity of 64 cells
7-198
TCT0
BufEPD
7-198
QueueCiCLP1
7-198
QueueMax
7-201
TCT1
BufCiCLP
7-201
TCT2
SBCiCLP
7-204
Data Sheet
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Operational Description ABM-3G Transfer Register Parameter Description See page
DH
Selects the hysteresis value for threshold evaluation If set, EPD is enabled If set, PPD is enabled Selects whether accepted packets or cells are counted This bit enables a modified EPD threshold evaluation for GFR traffic Defines maximum number of cells for this traffic class Defines threshold for the number of cells of this traffic class allowed in the associated Scheduler Initialization value Select value of peak rate limiter Weight of scheduler input in 16,320 steps Integer part of incremental value for Scheduler output rate Initialization value for SB counter Specify UTOPIA port for this scheduler Fractional part of incremental value for Scheduler output rate
7-207
EPDen PPDen SCNT
7-207 7-207 7-207
GFRen
7-207
TrafClassMax
7-207
TCT3
SBMax
7-207
QPT1
flags RateFactor
7-249 7-253 7-254 7-260
QPT2 WFQFactor IntRate SCTI Init UTOPIAPort SCTF
1)
7-260 7-269
FracRate
mixed threshold: EPD if enabled; otherwise, maximum threshold
Data Sheet
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Operational Description
4.2.1
Setup of Queues
Before assigning a connection to a new queue, it should be verified to be empty, as some cells could remain from the previous connection. A queue is emptied by setting it `invalid' while maintaining the scheduling parameters. An invalid queue will not except further cells; cells will be scheduled and de-queued, but not transmitted to the UTOPIA Interface. The queue length can be monitored by the external microprocessor.
Data Sheet
105
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Operational Description
4.2.2 4.2.2.1
Programming Queue Scheduler Rates and Granularities Scheduler Block Scheduler
The aggregate theoretical peak cell rate of the SBS is calculated as follows: SYSCLK PCR SBS = ---------------------32 [ cells s ] (3)
SYSCLK designates the core clock frequency. Each cell cycle needs 32 clock cycles. With the core SYSCLK = 51.84 [MHz] we have PCRSBS = 1620000 [cells/s]. This corresponds to 686,8 [Mbit/s] for 53 byte cells Note: Due to the need to perform internal SDRAM refresh cycles, the PCRSBS contains empty cells. A discussion on the empty cell rate PCR empty , which restricts the maximum scheduler block rate is contained in Section 4.2.2.4.
4.2.2.2
Programming the Scheduler Block Rates
For the peak cell rate of an SB we can have PCR SB = PCRSBS - PCR empty. In the following, let LC denote the logical channel assigned to an SB. Recall that a logical channel can subsume the whole output port or an reasonable subdivision. Let CCRSB denote the configured cell rate of an SB (i.e. the desired output cell rate). CCRSB(LC) = PCRLC must be chosen to match the peak cell rates of the LC as close as possible. Both permanent overload, leading to UTOPIA backpressure, and permanent underload, leading to poor channel utilization, should be avoided. Overall, the following holds
a CCR SB(LC) PCRUTOPIA
LC
(4)
Note: For short periods of time PCR SB as defined above can occur internally, independent of the particular CCR SB Deriving Internal Parameters from a Given CCRSB Internally the scheduler block output cell rate CCRSB is represented by two parameters: TSB(i)[13:0], the 14 bit integer division factor TSB(f)[7:0], the 8 bit fractional division factor These parameters are dimensionless and thus only indirectly represent the output rate. The following formulas show how to derive the two parameters assuming a given desired output rate CCRSB:
Data Sheet
106
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Operational Description First, a dimensionless floating point number TSB is calculated from CCRSB as follows: SYSCLK T SB = -------------------------------32 x C CR SB with TSB constrained internally to 1 T SB 2 14 - ----8 2 Therefore T SBmax = 16383,99609. Given a particular TSB, the internal parameters for the SB rate can be calculated: The integer division factor is calculated as: T SB ( i ) = T SB (7) (6) (5)
The fractional division factor is calculated as: T SB ( f ) = min ( a T SB - T SB n x 2
8
, 255 ) X
(8) designating the next integer
with X designating the integer part of X and greater or equal to X.
The integer and fractional division factor defined above are referred to as IntRate and FracRate in the register description. Refer to "USCTI/DSCTI" on Page 260 and "USCTFT/DSCTFT" on Page 269. The minimum cell rate possible in an SB is configured with TSBmax according to: SYSCLK MCR SB = -------------------------------32 x T SBmax (9)
The following Table 4-2 shows the rate limits for the SB as a function of the system clock SYSCLK. Table 4-2 Scheduler Block Rate Limits SYSCLK [MHz] 51.84 60 Cell cycle [ns] 617 533 PCRSB [cells/s] 1556000 1811000 MCRSB [cells/s] MBRSB [bit/s] (53) 98.8769 41924 114.4409 48523
In Table 4-3, the numerical values of the integer and fractional divisors are shown for different desired CCRSB. Due to the limited resolution of the internal rate representation,
Data Sheet
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Operational Description the delivered CCRSB measured at the scheduler output does not always match exactly the desired CCRSB. The delivered CCRSB is calculated by: SYSCLK CCR SB = --------------------------------------------------------T SB a fn 32 x a T SB a in + ----------------n 256 Table 4-3 SB Rate Calculation Examples for SYSCLK = 51.84 MHz TSB TSB(i) 335.4037 335 4.5878 4 1.1469 1 TSB(f) 104 151 38 Delivered CCRSB [cells/s] 4829.963 352953.191 1410612.245
o
(10)
Desired CCR SB [cells/s] 4830 353108 1412429
The deviation of the delivered CCR from the desired CCR is always less than 1 improves towards lower CCR. Scheduler Block Burst Limitation
/oo and
Per scheduler block cell bursts can occur due to previously unused cell cycles. Each SB has an event generator that determines when this SB should be served based on the programmed SB rates. Because several SB may share one UTOPIA interface, it can happen that events cannot be served immediately due to active cell transfers of previous events. Such 'unused cell cycles' are counted and can be used for later cell bursts allowing a near 100% SB rate utilization. Cell bursts due to this mechanism are not rate limited. The maximum burst size (MBS) generated due to previously counted 'unused cell cycles', is controlled by bit field MaxBurstS(3:0) in the range 0..15 cells (a minimum value of at least 1 is recommended). MaxBurst is programmed in registers "UECRI/DECRI" on Page 263. Per SB MBS dimensioning depends on the burst tolerance (BT) of subsequent devices (buffer capacity and backpressure capability). For example, if PHY(s) connected to the ABM-3G do not support backpressure and provide a 3-cell transmit buffer, a value in the range 1..3 is recommended to avoid PHY buffer overflows resulting in cell losses (e.g. typical for ADSL PHYs connected to the ABM-3G). If a PHY is connected that supports port specific backpressure to prevent its transmit buffers from overflowing or provides sufficient buffering, the maximum value of 15 can be programmed, guaranteeing a near 100% scheduler rate utilization.
Data Sheet
108
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
4.2.2.3
Programming the Common Real-Time Bypass
The Common Real-Time bypass (CRT) is denoted by the reserved logical queue identifier QID = 0. The rate assigned to the CRT bypass is programmed in the same way as the SB rates. The parameters CRTIntRate and CRTFracRate are described in registers "UCRTRI/DCRTRI" on Page 278 and "UCRTRF/DCRTRF" on Page 279.
4.2.2.4
Programming the SDRAM Refresh Empty Cell Cycles
The programming of the rate for the internal SDRAM refresh generator is done by calculating the integer and fractional parts of the dimensionless value Tempty according to the SB formulas (Equation (7) and Equation (8)). Tempty is constrained by the need to allow a minimum number of empty cell cycles for the internal SDRAM refresh generator according to: SYSCLK x RefreshPeriod T empty ------------------------------------------------------------------------32 x RefreshCycles Given values of RefreshPeriod = 64ms, RefreshCycles = 4096 then at SYSCLK = 51.84 MHz, Tempty = 25.3125, T empty(i) = 25, Tempty(f) = 80 This renders PCRempty = 64000 [cells/s] . In case additional bandwidth needs to be reserved (e.g. for multicast operation in subsequent devices), a second maximum condition for parameter TemptyMC can be derived depending on the empty cell rate required for multicast bandwidth reservation. The cell rate for the empty cell cycles PCRempty is programmed by setting Tempty(i) and Tempty(f), referred to as ECIntRate and ECFracRate in the corresponding registers "UECRI/DECRI" on Page 263 and "UECRF/DECRF" on Page 264. (11)
4.2.2.5
Programming the PCR Limiter
For each logical queue, an optional peak rate shaper can be programmed. Each cell passing the PCR limiter needs at least 2 cell cycles to emit. This limits the maximum PCR that can be shaped to: SYSCLK 1 -PCR R Smax = ------------------------ x -32 2 [ cells s ] (12)
The resolution of the PCR limiter is determined by the global parameter TstepC, common for all shapers in an ABM-3G core.
Data Sheet
109
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description TstepC is configured per direction by the field TstepC[2:0] described in "USCONF/ DSCONF" on Page 246. Internally the shaper use a derived value Tstep with the following interpretation: Tstep = 2
TstepC - 8
(13)
This renders Tstep in the range 1/2 ... 1/256. Smaller values for TstepC and in consequence Tstep imply lower shaping rates. Given a particular TP, the resulting PCR shaping rate is calculated as follows: 64 SYSCLK PCR R S = ------------------------ x Tstep x ------TP 32 Vice versa, for a given PCR, the corresponding TP value is calculated as: TP = SYSCLK 64 ------------------------ x Tstep x ------------------32 PCR RS (15) (14)
The value of parameter TP is constrained internally to: TP 2
16
-2
6
(16)
Therefore, TPmax = 65472. Though possible to specify, very low values of TP do not make much sense, because the shaper is limited by PCRRSmax in any case (see Equation (12)). Together with Equation (14) this leads to the following constraint on TP: TP max ( 1, Tstep x 128 ) The following special case must be considered: TP = 0 disables the shaper, connecting the queue directly to the level 1 schedulers (RR / WFQ). (17)
Data Sheet
110
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description Table 4-4 shows minimum PCR shaper rates for all the possible values of TstepC calculated at a SYSCLK of 51.84 MHz and 60 MHz with TPmax and Equation (14). Table 4-4 Minimum Shaper Rates as a Function of TstepC and SYSCLK SYSCLK = 51.84 [MHz] TstepC 0 1 2 3 4 5 6 7 1/Tstep 256 128 64 32 16 8 4 2 PCRRSmin [cells/s] 6.185 12.371 24.743 49.487 98.975 197.950 395.900 791.800 PBRRSmin [bit/s] 2622 5245 10491 20982 41965 83930 167861 335723 SYSCLK = 60 [MHz] PCRRSmin [cells/s] 7.160 14.320 28.639 57.278 114.555 229.110 458.219 916.437 PBRRSmin [bit/s] 3036 6072 12143 24286 48572 97143 194285 388569
The accuracy of the shaping rate is defined as: PCR in - PCR out acc PC R = -----------------------------------------PCRout (18)
with PCRin denoting the desired PCR and PCR out denoting the delivered PCR, which is always less than PCRin. PCRout is calculated by first deriving TP from PCRin in Equation (15) and then substituting TP in Equation (14). The accuracy improves towards lower shaping rates and higher values of TstepC. Note: The improvement is not monotonic and depends on the rounding error made at the calculation of TP. However, from the formulas given above, it can be deduced that the accuracy is always better than: PCR in acc PCR --------------------------------------------------------2 x SYSCLK x Tstep (19)
Data Sheet
111
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description Table 4-5 shows the accuracy of the shaping rate at some characteristic rates for three selected values of TstepC. Table 4-5 desired PCR 32 64 170 4830 101957 353108 Shaper Accuracy as a Function of desired PCR and TstepC accPCR at SYSCLK = 51.84 [MHz] TstepC = 0 0.000059 0.000138 0.000271 0.001774 0.006934 0.425621 TstepC = 4 not possible not possible 0.000009 0.000286 0.006934 0.034140 TstepC = 7 not possible not possible not possible 0.000007 0.001081 0.001288
Regarding the inevitable jitter (CDV) produced by the rate shaper due to its limited accuracy, it improves towards higher shaping rates and higher values of TstepC. The value of parameter TP derived above is programmed into the field RateFactor in register "UQPT2T0/DQPT2T0" on Page 253. Note: A value of 0 in field RateFactor disables both the PCR limiter and the leaky bucket shaper. Values other than 0 in field RateFactor are ignored for queues with an additional leaky bucket shaper enabled. The parameter TP defined there overrides. See Section 4.2.2.6.
4.2.2.6
Programming the Leaky Bucket Shaper
Regarding the Leaky Bucket Shaper, the formulas given previously in Section 4.2.2.5 apply accordingly when substituting SCR for PCR and TS for TP. In addition, given MBS, the parameter tauS is calculated as: TS - TP tauS = ( MBS - 1 ) x ae ---------------------o e 64 o with tauS constrained internally to: tauS 2
16
(20)
-2
10
(21)
Therefore, tauSmax = 64512.
Data Sheet
112
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description Given a particular tauS, the burst tolerance BT and the corresponding MBS produced by the leaky bucket shaper is calculated as: tauS 32 BT = --------------- x -----------------------Tstep SYSCLK and MBS = tauS x 64 1 + ------------------------TS - TP [ cells ] (23) [ sec ] (22)
The maximum BT has been derived from tauSmax and is shown in Table 4-6 for different values of TstepC and SYSCLK. Table 4-6 Maximum BT as a Function of TstepC and SYSCLK BT [s] TstepC 0 1 2 3 4 5 6 7 1/Tstep 256 128 64 32 16 8 4 2 SYSCLK = 51.84 [MHz] 10.192 5.097 2.548 1.274 0.637 0.318 0.159 0.079 SYSCLK = 60 [MHz] 8.807 4.403 2.201 1.100 0.550 0.275 0.137 0.068
Refer to "AVT Context Table: VBR Shaping (Table Layout)" on Page 97 for a detailed description and layout of the parameter fields.
Data Sheet
113
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
4.2.2.7
Guaranteed Cell Rates and WFQ Weight Factors
GCR WFQ = CCR SB - ECR RT ( SB )
The total WFQ scheduler rate is calculated as follows: (24)
with CCRSB being the configured SB rate as defined in Section 4.2.2.2 and ECRRT(SB) being the effective cell rate of the high priority RR scheduler in the SB. GCRWFQ is distributed to the queues in proportion to the queue's relative weight factor 1/ TWFQ. The guaranteed cell rate for connection i is calculated according to: GCR WFQ GCR i = ------------------------------------------------------------------------------------------------T WFQ ( i ) x 1 T WFQ ( k ) a
k Active Queues
(25)
with TWFQ constrained internally to: T WFQ 2
14
-2
6
(26)
Therefore, TWFQmax = 16320. The minimum guaranteed cell rate at a given GCRWFQ is therefore: GCR WFQ GCR min = ------------------------T WF Qmax (27)
Assuming a fixed given GCRmin, then for any given GCR >= GCR min the corresponding TWFQ can be calculated as: T WFQ = GCR min x T WFQmax ----------------------------------------------------GCR (28)
The integer function in equation above selects the next smaller value of the integer TWFQ, that is to say, the weight factor is higher than required and, thus, the queue is served slightly faster in order to guarantee the rate. Two special cases must be considered: TWFQ = 0 is used to assign the queue to the high priority round robin scheduler. TWFQ = 16383 is used to assign the queue to the low priority round robin scheduler. TWFQ is referred to as parameter WFQFactor in the register description "UQPT2T1/ DQPT2T1" on Page 254.
Data Sheet
114
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
4.2.3
ABM-3G Configuration Example
In this section, a popular mini-switch scenario (Figure 4-7) is used to describe the most important points for the software configuration of the ABM-3G. Among other things, the following fixed assignments can be made in software by the user: * * * * Assignment of Schedulers to PHYs and programming of Scheduler output rates Definition of the necessary traffic classes Assignment of the queues to the traffic classes Assignment of the queues (QIDs) to the Schedulers (SBIDs)
Assignment of Schedulers and Programming Output Rates The ABM-3G has 256 Schedulers (128 in the upstream direction and 128 in the downstream direction). In this example each xDSL device is assigned to a separate Scheduler (this guarantees each xDSL device a 2-Mbit/s data throughput without bandwidth restrictions caused by the other xDSL devices); then, 255 xDSL devices can be connected. The 256th Scheduler will be occupied by the E3 uplink to the public network. The assignment of the Schedulers to the PHYs is totally independent and even such a strong asymmetrical structure as in (Figure 4-7) can be supported. The output rates of the Schedulers must be programmed in such a way that the total sum does not exceed 622 Mbit/s (payload rate). From the example, the following result is derived: 255 x 2 Mbit/s + 1 x 34 Mbit/s = 544 Mbit/s 622 Mbit/s.
0 1
ADSL ADSL
Multiplex Network
2Mbit/s
ABM-3G
0
2Mbit/s
1
254
ADSL
UTOPIA
ALP
2Mbit/s 254 34Mbit/s 255
Uni directional mode
34 Mbit/s
E3
Uplink
= Scheduler, used as virtual PHYs ( UTOPIA PHYs)
Figure 4-7
Data Sheet
ABM-3G Application Example: DSLAM
115 2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description Definition of Necessary Traffic Classes The ABM-3G allows up to 16 traffic classes to be defined by Traffic Class Table RAM entry via the registers TCT0 to TCT3 (see Page 198f). In this example, there are 3 traffic classes: * CBR (real-time) = traffic class 1 * GFR (non-real-time) = traffic class 2 * UBR (non-real-time) = traffic class 3 Assignment of the Queues to the Traffic Classes Each queue must relate to a defined traffic class according to the Queue Configuration Table RAM entry via the TCID(3:0) bits of the QCT table. Assignment of the Queues (QIDs) to the Scheduler Blocks (SBIDs) Every Scheduler Block (SB) possesses a certain number of queues depending on the assignment by the user of the SBID(5:0) bits of register "QCT1" on Page 214. In the example, every ADSL device has four data connections so that four queues per SB are necessary. Each SB of the ABM-3G has one real-time queue and an arbitrary number of non-real-time queues. For SB 0..254, indicate that the first queue belongs to Traffic Class 1, the 2nd and 3rd Queue to Traffic Class 2, and the 4th Queue to Traffic Class 3. There are 1020 (1..1020) queues altogether for SB 0..254. The 256th SB must be able to serve the 255 xDSL devices (255 SBs and appropriate queues). Thus, SB 255 has 255 x 2 = 510 non-real-time queues as every SB from 0..254 possesses two GFR nonreal-time queues (GFR has a guaranteed minimum rate; thus, each GFR queue needs a per VC queueing). The 255 UBR queues of SBs 0..254 need only one UBR queue at the 256th SB as UBR has no guaranteed minimum rate. As every SB has only one realtime queue, the 255 real-time queues from SBs 0..254 flow into the one real-time queue of SB 255. Therefore, SB 256 needs the assignment of 510 (GFR) + 1 (UBR) + 1 (CBR) = 512 queues.
4.2.4
Normal Operation
In normal operation, no microprocessor interaction is necessary as the ABM-3G chip does all queueing and scheduling automatically. For maintenance purposes, periodically the microprocessor could read out the counters for buffer overflow events. Some overflow events may also be programmed as interrupts.
4.2.5
Bandwidth Reservation
Due to the WFQ Scheduler concept of the ABM-3G, the Connection Acceptance Check (CAC) is very simple: * Check if the Guaranteed Rate of the connection fits within the spare bandwidth of the Scheduler.
Data Sheet 116 2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description For the definition of the Guaranteed Rate, see Table 3-24. Mathematically, the CAC can be reduced to the following formulas: For all connections make sure that no overbooking of the configured scheduler output rate CCRout occurs, i.e.:
a GCRi = CCR out
i
(29)
For real-time connections, (CBR, rt-VBR) Equation (29) is the only condition required. For non-real-time connections or connections using the WFQ scheduler, additional conditions must be fulfilled. VBR and UBR+ connections must be setup in per VC queueing configurations, that is, an empty queue must be found for the connection. The Guaranteed Rate determines the weight of the queue.
4.2.5.1
Bandwidth Reservation Example
As an example, an access network multiplexer is assumed with ADSL lines and an E3 uplink. CBR and UBR+ connections are supported. A minimum Guaranteed Rate of GRmin = 19.2 Kbps is selected. This allows GR up to 314.57 Mbit/s with increasing granularity for higher values. This behavior is well suited to the Guaranteed Rates which are minimum or sustainable rates. The values for MCR and SCR will be well below 10 Mbit/s for public networks. In high speed LANs with high MCR and SCR values, a higher minimum rate could be selected. Additionally, it is assumed that three types of line interfaces (PHY) exist in the system: 34 Mbit/s for the uplink, ADSL rates of 8 Mbit/s downstream, and 0.6 Mbit/s upstream. For each PHY, a maximum possible weight factor 1/n exists: nmax = 9, nmax= 39, and nmax = 524, respectively. Two types of non-real-time connection are defined with Guaranteed Rates of 100 kbit/s and 20 Kbps with the weight factors 1/n, n100 = 3146 and n20 = 15730, respectively. The 100 Kbps connections would be used for the downstream direction, and the 20 Kbps connections for the upstream direction. Table 4-8 provides the maximum number of connections possible on each PHY.
Data Sheet
117
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
*
Table 4-8 PHY 34 Mbit/s 8 Mbit/s 0.6 Mbit/s
Number of Possible Connections per PHY GR = 100 Kbps 349 80 6 GR = 20 Kbps 1747 403 30
For example, if the maximum number of connections for each Subscriber is fixed (such as 5 data connections), the queues can be pre-configured for each Subscriber so that only the LCI assignment must be changed when a connection is setup or released.
4.2.6
Buffer Reservation
In addition to the bandwidth reservation, buffer space must be assigned by the appropriate setting of discard thresholds. Figure 4-9 shows an example of threshold configurations for four traffic classes (realtime, nrt-VBR, GFR, UBR).
2**18 BufMax
BufMaxNg (GFR) TrafClassMax (real-time) BufMaxNg (nrt-VBR) TrafClassMax (real-time) Shared by real-tim e, GFR and nrt-VBR Shared by real-time and GFR
TrafClassMax (GFR)
BufMaxNg (UBR)
Shared by all TrafClassMax (nrt-VBR)
Sum of guaranteed buffer
0
Figure 4-9
Example of Threshold Configuration
Data Sheet
118
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
4.2.7
Support of Standard ATM Service Categories
The following sections provide some insight into how the ABM-3G supports connections belonging to the well known ATM Forum service categories.
4.2.7.1
CBR Connections
These connections should use the real-time bypass of the respective scheduler block. However, if two priority levels for real-time connections must be offered, a slightly lower real-time performance can be achieved by using the WFQ scheduler with maximum weight. In this case, the bandwidth must fit into the WFQ scheduler (conditions (1) and (2) in "Bandwidth Reservation" on Page 116).
4.2.7.2
rt-VBR Connections
These connections can be treated like CBR connections with a guaranteed cell rate less than or equal to the Peak Cell Rate (PCR). Depending on the behavior of the sources, a statistical benefit could be obtained by reserving less than PCR. As an example, assume 1000 connections with compressed voice are multiplexed on a link. PCR is 32 Kbps, but on average only 16 Kbps. SCR is 8 Kbps. Hence, instead of reserving 32 Mbit/s for the ensemble of connections, only 16 Mbit/s must be reserved. The large number of connections guarantees that the mean sum rate of 16 Mbit/s is exceeded only with a negligible probability.
4.2.7.3
nrt-VBR Connections
For these connections, the three parameters PCR, SCR, and MBS are given. One queue is reserved for each nrt-VBR connection with SCR programmed as the weight of the respective Scheduler queue. The maximum queue size is set to MBS plus approximately 100 cells for cell level bursts. If the buffer space reserved for nrt-VBR connections is set to the sum of all MBS, it is guaranteed that no cell is lost. However, with a large number of nrt-VBR connections, the total reserved buffer can be smaller with a negligible number of cell losses. For the PCR, no adjustment is necessary as the rates of the queues of a Scheduler always adjust automatically to the maximum possible values. As an option for network endpoints, for both rt-VBR and nrt-VBR the PCR and SCR may be shaped by the PCR limiter and SCR leaky bucket shaper as described in Chapter 3.4.2.4. This is useful at network boundaries (UNI/NNI) to provide conforming traffic to the subsequent policer.
4.2.7.4
UBR+ Connections
UBR+ connections are UBR connections with MCR. They must be setup in individual queues with the weight factor guaranteeing the MCR.
Data Sheet 119 2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description To enhance the overall throughput, the EPD/PPD function is enabled.
4.2.7.5
GFR Connections
GFR Connections are setup like UBR+ connections with a Guaranteed Rate in individual queues, with the weight factor guaranteeing the rate for the high-priority packets. The threshold for the discard for low-priority packets must be set accordingly.
4.2.7.6
UBR Connections
As described in "Bandwidth Reservation" on Page 116, one queue per Scheduler is reserved for UBR connections with the smallest weight assigned. All UBR connections share this queue. EPD/PPD can be enabled as the relevant parameters are stored per connection (LCI table).
4.2.7.7
Generic Service Classes
Besides the standard ATM Forum service categories, other generic service classes can be flexibly supported by the ABM-3G. Quality of service differentiation in terms of absolute and relative guarantees can be achieved for any traffic stream that is segmentable into the ABM-3G cell format.
Data Sheet
120
2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
4.3
Connection Teardown Example
Teardown of Queues Disabling a queue via the queue-disable bit does not clear the cells in the queue, but: * The acceptance of the queue for new cells is disabled * The queue is still served, but the cells are discarded internally Normally, at the time a queue is cleared, there will be no more cells in the queue. This can be checked by reading the queue length. In case of a highly filled queue which is served slowly, the time to empty the queue could be long. To deplete the queue more quickly, its weight can be increased temporarily. However, because the discarded cells produce idle times on the UTOPIA output, the chosen weight factor should not be too high.
4.4
AAL5 Packet Insertion/Extraction
Refer to Chapter 3.2.3 for a more general description.
4.4.1
AAL5 Packet Insertion
First, the header octets are assembled from the VPI, VCI and/or LCI and written to the corresponding registers UA5TXHD0/DA5TXHD0 and UA5TXHD1/DA5TXHD1. The CPCS-UU and CPI are also provided to register UA5TXTR/DA5TXTR. The packet payload length is written to UA5TXCMD/DA5TXCMD together with the AAL5EN flag. Four octets of payload are written to the two data registers UA5TXDAT0/DA5TXDAT0 and UA5TXDAT1/DA5TXDAT1. The Status register UA5SARS/DA5SARS should be read afterwards to check the current state of the assembly unit. The assembly of the cells is done without interaction of the microprocessor.
4.4.2
AAL5 Packet Extraction
If an AAL5 interrupt indicates that an AAL5 packets has arrived first the cell header should be read. Before each access to the data registers the status register UA5SARS/ DA5SARS should be read to get the current status of the extraction unit. As long as the AAL5 status register does not indicate End of Packet (PE), the payload can be received from the data registers UA5RXDAT0/DA5RXDAT0 and UA5RXDAT1/ DA5RXDAT1. This data registers should always be read together. If the PE flag is set the next read accesses to the both data registers will return the last payload octets. After this access the Status register still contains the PE flag but additionally a length information of the packet stored in the OV flags. Again the data registers are read to get the trailer of the packet (CPCS-UU and CPI) and the Status Byte. Depending on the packet length there are four possibilities for the mapping of these octets to the two data registers, indicated by the OV flags. The four cases are depicted in Figure 4-10.
Data Sheet 121 2001-12-17
ABM-3G PXF 4333 V1.1
Operational Description
*
RXDAT0 OV=00B n CPCSUU
RXDAT1 CPI Status
RXDAT0 -
RXDAT1 -
RXDAT0 OV=01B n -1 n
RXDAT1 CPCSUU CPI
RXDAT0 Status -
RXDAT1 -
RXDAT0 OV=10B n -2 n -1
RXDAT1 n CPCSUU
RXDAT0 CPI Status
RXDAT1 -
RXDAT0 OV=11B n -3 n -2
RXDAT1 n -1 n
RXDAT0 CPCSUU CPI
RXDAT1 Status -
PE=1 OV=invalid
PE=1 OV=valid
Figure 4-10 AAL5 Extraction: End of packet, Trailer and Status Byte The Status Byte returns some information about the received packet: Bit 7 unused 6 5 END 4 ICHN 3 CLP 2 CGST 1 UUE 0 CPIE
Table 4-11 Flag END
AAL5 Status Byte Description Error bit. Set if a cell with a different header is received before the end of a packet. Should not occur if VC merge is used, but the user might have a programming error. Invalid channel number. Indicates a change of the cell header before end of packet. CLP=1 in at least one cell of the packet Congestion occurred, i.e. PT(1)=1 in at least one cell of the packet CPCS-UU value is not 0; no other action CPI value is not 0; no other action
122 2001-12-17
ICHN CLP CGST UUE CPIE
Data Sheet
ABM-3G PXF 4333 V1.1
Operational Description Note: If a packet is extracted too slowly, an MUXOV interrupt might occur. To avoid this, either mask the MUXOV interrupt during extraction or reduce the output rate of the scheduler.
4.5
Exception Handling
The ABM-3G provides a set interrupts classified as: * Fatal * Notification * Normal Fatal interrupts It is recommended to reset the device upon occurrence of a `fatal interrupt' which is generated by the ABM-3G detecting internal consistency violations. Notifications/Normal interrupts * Control interrupts for activation/de-activation of VC-merge groups * Control interrupts for activation/de-activation of `dummy' queues
Data Sheet
123
2001-12-17
ABM-3G PXF 4333 V1.1
Interface Description
5
5.1
Interface Description
UTOPIA L2 Interfaces (PHY side)
The UTOPIA Interface to the PHY is ATMF UTOPIA Level 2 and Level 1 compliant. The interface can be configured in Master or Slave Mode. Internal UTOPIA FIFOs guarantee Head-of-Line blocking-free operation in both modes. Each interface direction (receive and transmit) is independently clocked. The PHY side and backplane side UTOPIA Interfaces are identical with minor exceptions as described in the subsequent chapters.
5.1.1
URXU: UTOPIA Receive Upstream (PHY side)
The UTOPIA Receive Interface supports up to 48 PHY addresses that can be individually enabled. In Master Mode and Slave Mode, 48 PHYs are supported in four groups (4*12 scheme). Note: In Slave Mode, the interface responds to all enabled port addresses.
*
URXDATU(15:0) UTOPIA Receive Upstream (PHY side) Master Mode Cell Handler (Upstream) URXSOCU URXPRTYU URXCLKU
4 cell FIFO
Addressing up to 4*12 PHYs: PHY 3 Address PHY 2 0..11 Address PHY 1 0..11 Address PHY 0 0..11 Address 0..11
Backpressure
URXADRU(4:0) URXENBU(3:0) URXCLAVU(3:0)
Figure 5-1
*
UTOPIA Receive Upstream Master Mode
URXDATU(15:0) UTOPIA Receive Upstream (PHY side) Slave Mode
Cell Handler (Upstream)
URXSOCU URXPRTYU URXCLKU URXADRU(4:0) URXENBU(3:0) URXCLAVU(3:0) Responding to up to 4*12 addresses
4 cell FIFO
Backpressure
Figure 5-2
Data Sheet
UTOPIA Receive Upstream Slave Mode
124 2001-12-17
ABM-3G PXF 4333 V1.1
Interface Description Head of Line Blocking Avoidance The internal Cell Handler Unit accepts any cell from the common UTOPIA receive FIFO to either accept the cell or discard the cell depending on threshold decisions. Thus, no HOL blocking can occur. Optionally, internal thresholds can be enabled to generate backpressure to UTOPIA port groups in a fixed scheme: * * * * Threshold 0 effects ports Threshold 1 effects ports Threshold 2 effects ports Threshold 3 effects ports {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44} {1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45} {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46} {3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47}
In case of pending backpressure, a specific port reacts in the same way as being disabled: * Master Mode: A backpressured (or disabled) port is deleted from the polling scheme. * Slave Mode: A backpressured (or disabled) port does not generate a cell available signal indication. Note: The internal backpressure does only effect the polling/response scheme. The UTOPIA receive FIFO is served in any case to avoid HOL blocking.
5.1.2
UTXD: UTOPIA Transmit Downstream (PHY side)
The UTOPIA transmit interface supports up to 48 PHY addresses that can be individually enabled. In Master Mode, 48 PHYs are supported in four groups (4*12 scheme). In Slave configuration, two polling modes are supported: * Up to 48 Ports in 4 groups (4*12 scheme) * Up to 31 Ports in 1 group (1*31 scheme) Note: In Slave Mode, the interface responds to all enabled port addresses in either scheme. A cell buffer pool of 64 cells is provided for UTOPIA port specific queues. The number of enabled ports determines the queue length that can be configured. At least one cell buffer per queue is provided.
Data Sheet
125
2001-12-17
ABM-3G PXF 4333 V1.1
Interface Description
*
UTOPIA Transmit Downstream (PHY side) Master Mode
Cell Handler (Downstream)
64 Cells Buffer Pool: Logical Queues per UTOPIA port
UTXDATD(15:0) UTXSOCD UTXPRTYD UTXCLKD UTXADRD(4:0) UTXENBD(3:0) UTXCLAVD(3:0)
Addressing up to 4*12 PHYs: PHY 3 Address PHY 2 0..11 Address PHY 1 0..11 Address PHY 0 0..11 Address 0..11
Queue Specific Backpressure Scheduler Block
Figure 5-3
UTOPIA Transmit Downstream Master Mode
UTOPIA Transmit Downstream (PHY side) Slave Mode
Cell Handler (Downstream)
64 Cells Buffer Pool: Logical Queues per UTOPIA port
UTXDATD(15:0) UTXSOCD UTXPRTYD UTXCLKD UTXADRD(4:0) UTXENBD(3:0) UTXCLAVD(3:0)
Queue Specific Backpressure Scheduler Block
Responding to a) up to 4*12 addresses b) up to 1*31 addresses (UTXENBD(0), UTXCLAVD(0) only)
Figure 5-4
UTOPIA Transmit Downstream Slave Mode
Head of Line Blocking Avoidance The internal Cell Handler Unit forwards cells to UTOPIA port-specific queues. In case of a filled queue, queue-specific backpressure is signalled to all schedulers that are associated to that queue/port prohibiting further cell emits. Thus no HOL blocking can occur.
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5.1.3
Table 5-1 Address
UTOPIA Port/Address Mapping (PHY side)
Port/Address Mapping Group 1 Group 2 Group 3 Slave Mode 1*31 30 ... 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode 4*12 and Master Modes
Table 5-1 describes the mapping of UTOPIA addresses and groups to port numbers. Port Number Group 0
30 ... 12 11 10 9 8 7 6 5 4 3 2 1 0
... 11 10 9 8 7 6 5 4 3 2 1 0
... 23 22 21 20 19 18 17 16 15 14 13 12
... 35 34 33 32 31 30 29 28 27 26 25 24
... 47 46 45 44 43 42 41 40 39 38 37 36
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Interface Description
5.1.4
Functional UTOPIA Timing (PHY side)
The functional timing is compatible to ATMF UTOPIA Level 2 standard [4] and ATMF UTOPIA Level 1 standard [3] respectively. Remark 1 The ABM-3G UTOPIA Interfaces in Master Mode always introduce at least 1 idle clock between transmission or reception of subsequent ATM cells. Remark 2 The ABM-3G UTOPIA Interfaces in Level 1 Slave Mode do not support constant active enable signals UTXENBi/URXENBi (i = {D(Downstream); U(Upstream)}). The enable signals must be deasserted with each cell cycle.
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Interface Description
5.1.5
UTOPIA Master Mode Polling Scheme (PHY side)
The polling scheme is based on a port priority list. A serviced port is automatically moved to the end of the priority list. The priority list port sequence is based on incrementing addresses; for a given address, the port numbers are in increasing order: Table 5-2 Address Sequence Priority Port Polling Sequence 0 0 decreasing priority -> 1 12 24 36 1
max Prio.
2 13 25 37 2
min Prio.
3 14 26 38 3
4 15 27 39 4
decreasing priority ->
Example Assume Port 25 (printed bold in example pattern) is at the top of the priority list and gets serviced. Now, the list top pointer is moved to the next entry which is Port 37 (i.e. Port 25 becomes the end of the list). Note: Disabled or internally backpressured ports are deleted from the priority list. Polling operation of Receive and Transmit interfaces is independent of each other.
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Interface Description
5.1.6
UTOPIA Cell Format (PHY side)
The following sections describe the cell format expected by the ABM-3G, depending on the selected mapping mode. Transmitted cells have the same format. The ABM-3G may modify the LCI field (VC-Merge function), depending on the configuration. For internal use, also field UDF2 may be modified. The CRC10 field gets recalculated accordingly.
5.1.6.1
Table 5-3 bit: 0 1 2 3 4 ... 26 15
UTOPIA Level 2 Standard Cell Formats
Standardized UTOPIA Level 2 Cell Format (16-bit) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPI(11:0) VCI(11:0) UDF1 Payload Octet 1 Payload Octet 3 : Payload Octet 47 UDF2
VCI(15:12) PT(2:0) Payload Octet 2 Payload Octet 4 : Payload Octet 48
CLP
Note: All Fields According to Standards, Unused Octets Shaded Table 5-4 bit: 0 1 2 3 4 ... 25 26 UDF1 OAM Type(3:0) : Function Specific Octet 44 Reserved CRC10 Function Type(3:0) Function Specific Octet 2 15 14 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPI(11:0) VCI(11:0) UDF2
VCI(15:12) PT(2:0) Function Specific Octet 1 Function Specific Octet 3 : Function Specific Octet 45
CLP
Note: All fields according to standards, unused octets are shaded.
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Interface Description
5.1.6.2
LCI Mapping Mode: VPI Mode
In Mapping Mode `VPI', the ABM-3G expects a 12-bit local connection identifier in the location of the VPI field. Mapping Mode `VPI' is configured via bit field LCIMOD(1:0)='00' in Register "MODE1" on Page 312. Table 5-5 bit: 0 1 2 3 4 ... 26 UDF1 Payload Octet 1 Payload Octet 3 : Payload Octet 47 15 14 Standardized UTOPIA Level 2 Cell Format (16-bit) 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCI(11:0) VCI(11:0) UDF2
VCI(15:12) PT(2:0) Payload Octet 2 Payload Octet 4 : Payload Octet 48
CLP
5.1.6.3
LCI Mapping Mode: VCI Mode
In Mapping Mode `VCI', the ABM-3G expects a 16-bit local connection identifier in the location of the VCI field. Mapping mode `VCI' is configured via bit field LCIMOD(1:0)='01' in Register "MODE1" on Page 312. Table 5-6 bit: 0 1 2 3 4 ... 26 UDF1 Payload Octet 1 Payload Octet 3 : Payload Octet 47 15 14 Standardized UTOPIA Level 2 Cell Format (16-bit) 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPI(11:0) LCI(11:0) UDF2
LCI(15:12) PT(2:0) Payload Octet 2 Payload Octet 4 : Payload Octet 48
CLP
Since the ABM-3G supports 16 K connections, the MSB bits 15 and 14 of the LCI must match the selected quarter segment. Otherwise, the cells are automatically forwarded to the global real time bypass queue (Queue 0) and may be handled by a subsequent ABM-3G device.
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5.1.6.4
LCI Mapping Mode: Infineon Mode
In Mapping Mode `Infineon', the ABM-3G expects a 16-bit local connection identifier in the location of the VPI field and the UDF1 byte as shown below. Mapping Mode `Infineon' is configured via bit field LCIMOD(1:0)='10' in Register "MODE1" on Page 312. Table 5-7 bit: 0 1 2 3 4 ... 26
LCI(13:12)
Standardized UTOPIA Level 2 Cell Format (16-bit) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15
LCI(11:0) VCI(11:0) transparent Payload Octet 1 Payload Octet 3 : Payload Octet 47
LCI(15:14)
VCI(15:12) PT(2:0) UDF2 Payload Octet 2 Payload Octet 4 : Payload Octet 48
CLP
Since the ABM-3G supports 16 K connections, the MSB bits 15 and 14 of the LCI must match the selected quarter segment. Otherwise the cells are automatically forwarded to the global real time bypass queue (Queue 0) and may be handled by a subsequent ABM-3G device.
5.1.6.5
LCI Mapping Mode: Address Reduction Mode
In Mapping Mode `Address Reduction', the ABM-3G generates a 16-bit local connection identifier based on the marked bit fields. Mapping Mode `Address Reduction' is configured via bit field LCIMOD(1:0)='11' in Register "MODE1" on Page 312. Table 5-8 bit: 0 1 2 3 4 ... 26 transp. 15 14 Standardized UTOPIA Level 2 Cell Format (16-bit) 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPI(11:0) VCI(11:0) optional PNUT(5:0) Payload Octet 1 Payload Octet 3 : Payload Octet 47 UDF2
VCI(15:12) PT(2:0) Payload Octet 2 Payload Octet 4 : Payload Octet 48
CLP
Data Sheet
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Interface Description To generate an Local Connection Identifier (LCI), programmable parts of the fields VCI and VPI optionally supplemented by the UTOPIA port number can be used as basis. The UTOPIA port number is internally provided either by side-band signals (no modifications to ATM cell) or mapped into either the UDF2 field of the cells. In this case, the respective UDF2 field is not transparent. Address Reduction Mode is described in Chapter 3.2.4.
Data Sheet
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Interface Description
5.2 5.2.1
UTOPIA L2 Interface (Backplane side) URXD: UTOPIA Receive Downstream (Backplane side)
The UTOPIA Receive Downstream Interface is identical to the UTOPIA Receive Upstream Interface as described in Chapter 5.1.1. Standard Exceeding UTOPIA Feature To support system architectures that require a bandwidth overprovisioning from the backplane, the URXD can be operated up to 60 MHz which corresponds to a data rate of 795 Mbit/s received from the backplane. This provides an overprovisioning factor of 1.32 to OC12 data rate on the line side as described in Chapter 3.1.1.
5.2.2
UTXU: UTOPIA Transmit Upstream (Backplane side)
The UTOPIA Transmit Upstream Interface is identical to the UTOPIA Transmit Downstream Interface as described in Chapter 5.1.2.
5.2.3
UTOPIA Port/Address Mapping (Backplane side)
The UTOPIA Port/Address mapping (Backplane side) is identical to the UTOPIA Port/ Address Mapping as described in Chapter 5.1.3.
5.2.4
Functional UTOPIA Timing (Backplane side)
The functional timing is compatible to ATMF UTOPIA Level 2 standard [4] and ATMF UTOPIA Level 1 standard [3] respectively. Remark 1 The ABM-3G UTOPIA Interfaces in master mode always introduce at least 1 idle clock between transmission or reception of subsequent ATM cells. Remark 2 The ABM-3G UTOPIA Interfaces in Level 1 Slave Mode do not support constant active enable signals UTXENBi/URXENBi (i = {D(Downstream); U(Upstream)}). The enable signals must be deasserted with each cell cycle.
5.2.5
UTOPIA Master Mode Polling Scheme (Backplane side)
The UTOPIA Polling scheme (Backplane side) is identical to the UTOPIA Polling scheme as described in Chapter 5.1.5.
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Interface Description
5.2.6
UTOPIA Cell Format (Backplane side)
The UTOPIA Polling scheme (Backplane side) is identical to the UTOPIA Polling scheme as described in Chapter 5.1.6.
5.3
MPI: Microprocessor Interface
The ABM-3G Microprocessor Interface is a generic asynchronous 16-bit slave-only interface that supports Intel and Motorola style control signals. The interface is `ready' signal controlled.
5.3.1
Intel Style Write Access
MPADR(7:0) MPCS MPWR MPRDY MPDAT(15:0) MPMODE
Figure 5-5
Intel Style Write Access
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Interface Description
5.3.2
Intel Style Read Access
MPADR(7:0) MPCS MPRD MPRDY MPDAT(15:0) MPMODE
Figure 5-6
Intel Style Read Access
5.3.3
Motorola Style Write Access
MPADR(7:0) MPCS (MPRD) DS (MPWR) R/W (MPRDY) RDY (DTACK) MPDAT(15:0) MPMODE
Figure 5-7
Motorola Style Write Access
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Interface Description
5.3.4
Motorola Style Read Access
MPADR(7:0) MPCS (MPRD) DS (MPWR) R/W (MPRDY) RDY (DTACK) MPDAT(15:0) MPMODE
Figure 5-8
Motorola Style Read Access
5.3.5
Interrupt Signals
The ABM-3G asserts its interrupt signals MPINT and MPINTD if non-masked interrupt events are pending in the respective interrupt status registers. Interrupt signals are deasserted in case all events are cleared by writing `1' to pending interrupt bits (e.g. write 0xFFFFH to the respective Interrupt Status Register). This allows edge sensitive interrupt implementations. Interrupt signals are of type `Open Drain' to allow wired-or implementations sharing one interrupt signal with other devices.
Data Sheet
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Interface Description
5.4 5.4.1
External RAM Interfaces RAM Configurations
The ABM-3G device uses synchronous dynamic RAM (SDRAM) for the storage of ATM cells and synchronous static RAM (SSRAM) for the storage of cell pointers. Two SDRAM Interfaces and one SSRAM Interface are provided. Each of the two SDRAM Interfaces is associated with one of the ABM Cores. The SSRAM Interface is shared by both ABM-3G Cores. All RAM Interfaces are operated with the system clock provided by the ABM-3G: Table 5-9 Cell Pointer SSRAM External RAM Sizes Min. Required Upstream Cell SDRAM UBMTH UpMin. stream Required Buffer Downstream Cell SDRAM 128 Mb e.g. 2*(4Mb*16) 64 Mb e.g. 1*(2Mb*32) 32 Mb none 3FFFFH 256K cells 1FFFFH 128K cells 0FFFFH 64K cells 3FFFFH 256K cells 1FFFFH 128K cells 0FFFFH 64K cells DBMTH Downstream Buffer
e.g. 128 Mb 512 k x 32 bit e.g. 2*(4Mb*16) e.g. 64 Mb 256 k x 32 bit e.g. 1*(2Mb*32) e.g. 32 Mb 128 k x 32 bit e.g. 128 Mb 256 k x 32 bit e.g. 2*(4Mb*16) e.g. 64 Mb 128 k x 32 bit e.g. 1*(2Mb*32) e.g. 64 k x 32 bit 32 Mb
3FFFF H 256K cells
1FFFF H 128Kk cells 0FFFF H 64K cells 0000 H 0
none
0000 H
0
none
0000 H
0
Note: The upstream cell storage RAM must always be connected.
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Interface Description The minimum required width of the cell pointer SSRAM is in the range 16..20 bits depending on the selected Cell Storage Size and additional feature configurations: Table 5-10 SSRAM Configuration Examples Stored Address Pointer Width 18 18 18 17 17 17 16 16 16 Feature Bits Min. SSRAM Width Cell Storage RAM Enabled Features cell capacity (each) 256K VBR.2/3 + EOP marking EOP marking none 128K VBR.2/3 + EOP marking EOP marking none 64K VBR.2/3 + EOP marking EOP marking none
2 1 0 2 1 0 2 1 0
20 19 18 19 18 17 18 17 16
Note: VBR.2/3 represents VBR shaping function 2 and 3 requiring one additional bit storage in the CPR for the CLP bit. EOP marking represents one additional bit storage in the CPR for End-of-Packet indication required by EPD/PPD and VC-Merge operation. Table 5-11 gives an example of supported SDRAM configuration:
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*
Table 5-11 Type
SDRAM Configuration Examples Configuration per Direction 1 SDRAM: 8-bit column address 10-bit row address 2-bit bank select Note: This Configuration supports only 128k cells storage per direction.
512k * 32 (4 bank) (64Mb Type)
1Mb * 16 (4 bank) (64Mb Types)
2 SDRAM: 8-bit column address 12-bit row address 2-bit bank select Note: This Configuration supports 256k cells storage per direction.
2Mb * 16 (4 bank) (128Mb Types)
2 SDRAM: 9-bit column address 12-bit row address 2-bit bank select Note: This Configuration supports 256k cells storage per direction. (50% memory remains unused)
4Mb * 16 (4 bank) (256Mb Types)
2 SDRAM: 9-bit column address 12-bit row address (13) 2-bit bank select Note: This Configuration supports 256k cells storage per direction. (75% memory remains unused; one of the 13 memory address bits remains unused)
Note: Both CSR Interfaces support 8-bit and 9-bit column address width SDRAM types (see register "MODE2" on Page 315). Table 5-12 gives an example of supported SSRAM configurations:
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*
Table 5-12 Type SSRAM 1 1 2
SSRAM and SDRAM Type Examples Configuration
Micron MT58V512V32F (flow through) Infineon HYB39S64160BT Infineon HYB39S256160BT
512k * 32 4 banks * 1M * 16 4 banks * 4M * 16
SDRAM
5.5
Test Interface
The boundary scan functionality is implemented according to IEEE 1149.1, using a 5-pin test access port.
5.6 5.6.1
Clock and Reset Interface Clocking
The ABM-3G supports different clock domains and clock generation configurations. "Clocking System" on Page 52 provides the details.
5.6.2
Reset
The Reset signal can be asserted anytime asynchronously to the system clock. After detecting an active reset, the ABM-3G starts internal initialization processes and resets all registers to their reset value. Chapter "Reset System" on Page 54 provides the details. Note: Internal and external RAM initialization must be initiated by software via register "MODE1" on Page 312.
Data Sheet
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Memory Structure
6
Memory Structure
The ABM-3G is a slave device in relation to the microcontroller bus and provides a set of 256 16-bit wide registers. Internal tables are accessed via dedicated transfer registers (see Figure 7-1). Typically, the register structure is mapped into the memory address space of the local controller.
Data Sheet
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Register Description
7
Register Description
This chapter provides both an overview of the ATM Buffer Manager ABM-3G Register Set and detailed register descriptions and Table Access descriptions.
7.1
Overview of the ABM-3G Register Set
Control and operation of the ABM-3G chip can be done by directly configuring Status Registers or, to a large extent, by programming the internal tables. Access to these tables is not direct, but occurs via Transfer Registers and Transfer Commands. Any transfer must be prepared by writing appropriate values to the Transfer Registers. Bit positions named 'don't Write' must be masked by writing 1 to the corresponding bit positions in the Mask Register. This avoids overwriting these table bit positions with the Transfer Register contents, which may cause fatal malfunction. The specific table position which should be modified with the Transfer Register contents is selected via Register WAR. Transfer is started by writing the table address to Register MAR and also setting the 'Start' bit. The ABM-3G device will reset the 'Start' bit after transfer completion. The ABM-3G contains the following internal tables for configuration: * * * * * * * LCI Table (LCI) Traffic Class Table (TCT) Queue Configuration Table (QCT) Queue Parameter Table 1 (QPT1) Queue Parameter Table 2 (QPT2) Scheduler Block Occupancy Table (SBOC) Scheduler Block Rate Tables (consisting of 4 tables): - SCTI Upstream - SCTI Downstream - SCTF Upstream - SCTF Downstream * Merge Group Table (MGT) * VBR Table (AVT) Figure 7-1 gives an overview of all (user accessible) tables and related control/transfer/ mask registers:
Data Sheet
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Register Description
*
LCI Table MAR = 00d Mask Registers
TCT Table MAR = 01d
QCT Table MAR = 02d
SBOC Table MAR = 03d
MGT Table MAR = 07d
Common Mask Register Set: LCI0 LCI1 LCI2
MASK6
MASK5 MASK2 QCT0 QCT1 QCT2 QCT3 QCT4 QCT5 QCT6
MASK4 MASK1 SBOC0 SBOC1 SBOC2 SBOC3 SBOC4
MASK3 MASK0 MGT0 MGT1 MGT2
Data Transfer Registers
TCT0 TCT1 TCT2 TCT3
Common Table Access Control Registers: MAR WAR
Data Transfer Registers
ERCT1 ERCT0
UQPT1T1 UQPT1T0
UQPT2T3 UQPT2T2 UQPT2T1 UQPT2T0
DQPT1T1 DQPT1T0
DQPT2T3 DQPT2T2 DQPT2T1 DQPT2T0
USCTFT
DSCTFT
Mask Registers
ERCM1 ERCM0
UQPTM3 UQPTM2
UQPTM2 UQPTM0
DQPTM3 DQPTM2
DQPTM2 DQPTM0
USCTFM
DSCTFM
AVT Table MAR = 10d
QPT1 Table Upstream MAR = 16d
QPT2 Table Upstream MAR = 17d
QPT1 Table Downstr. MAR = 24d
QPT2 Table Downstr. MAR = 25d
SCTF Table Upstream MAR = 23d
SCTF Table Downstr. MAR = 31d
SCTI Table Upstream
SCTI Table Downstr.
no Mask USCTI
no Mask DSCTI
SCTI Table Access Control Registers: DSADR USADR
Figure 7-1
Table Access Overview
The Status Registers and Transfer Registers are described below in Table 7-2. Offset addresses are 16-bit word addresses. in order to prevent malfunctions and to guarantee upwards compatibility to future versions of the device, performing Write accesses to 'Reserved Register' addresses is not recommended.
Data Sheet
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Register Description Internal table entries contain bit fields for internal device operation only. Table 7-1 identifies the color conventions used for the various types of fields described in this register chapter: Table 7-1 Color Color Convention for Internal Table Field Illustration Meaning Grey shaded fields are 'unused'. Reading these fields will return '0'. Green shaded fields require attention by CPU. They can be written or read by CPU; usage depends on the respective field description. Typically green fields must be written for initialization and configuration or read for status query. Blue shaded fields require/allow READ attention by CPU. Typically blue fields provide counter or status information. The CPU MUST NOT write to blue fields. Red shaded fields are for device internal use only and require NO attention by CPU. The CPU MUST NOT write to red fields.
*
Table 7-2 Addr (hex)
ABM-3G Registers Overview Description Reset P value (hex) 0000
See page
Register
Cell Flow Test Registers 01/11 UCFTST/ DCFTST URCFG/ DRCFG UA5TXHD0/ DA5TXHD0 UA5TXHD1/ DA5TXHD1 UA5TXDAT0/ DA5TXDAT0 Upstream/Downstream Cell Flow Test Registers Upstream/Downstream SDRAM Configuration Registers Reserved Register Reserved Register Upstream/Downstream AAL5 Transmit Header 0 Registers Upstream/Downstream AAL5Transmit Header 1 Registers Upstream/Downstream AAL5Transmit Data 0 Registers
145
R/W 156
SDRAM Configuration Registers 02/12 03/13 04/14 05/15 06/16 07/17 0033 0000 0000 0000 0000 0000 R/W 157 R R -
Cell Insertion/Extraction and AAL5 Control Registers R/W 158 R/W 160 R/W 162
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) 08/18 09/19 0A/1A 0B/1B 0C/1C 0D/1D 0E/1E 0F/1F ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000 0000 0000 0000 0000
See page
Register
UA5TXDAT1/ DA5TXDAT1 UA5TXTR/ DA5TXTR UA5TXCMD/ DA5TXCMD UA5RXHD0/ DA5RXHD0 UA5RXHD1/ DA5RXHD1 UA5RXDAT0/ DA5RXDAT0 UA5RXDAT1/ DA5RXDAT1 UA5SARS/ DA5SARS UBufferOcc DBufferOcc UBufferOccNg DBufferOccNg UBufMax DBufMax UMAC DMAC UMIC DMIC CLP1DIS
Upstream/Downstream AAL5 Transmit Data 1 Registers Upstream/Downstream AAL5 Transmit Trailer Registers Upstream/Downstream AAL5 Transmit Command Registers Upstream/Downstream AAL5 Receive Header 0 Registers Upstream/Downstream AAL5 Receive Header 1 Registers Upstream/Downstream AAL5 Receive Data 0 Registers Upstream/Downstream AAL5 Receive Data 1 Registers Upstream/Downstream AAL5 SAR Status Registers Upstream/Downstream Buffer Occupation Registers Up-/Downstream Non-Guaranteed Buffer Occupation Registers
R/W 163 R/W 164 R/W 165 R/W 166 R/W 168 R/W 170 R/W 171 R/W 172
Buffer Occupation Counter Registers 20 21 22 23 24 25 26 27 28 29 2A 0000 0000 0000 0000 0000 0000 0000 0000 R R R R 174 174 175 175
Buffer Threshold and Occupation Capture Registers Upstream/Downstream Buffer Maximum Threshold Registers Upstream/Downstream Maximum Occupation Capture Registers Upstream/Downstream Minimum Occupation Capture Registers CLP1 Discard Global Threshold Registers R/W 176 R/W 176 R R 178 178 179 179
FFFF R FFFF R 0000
R/W 180
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Register Description Table 7-2 Addr (hex) ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000
See page
Register
Configuration Register 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D CONFIG UUBPTH0 UUBPTH1 UUBPTH2 UUBPTH3 UBPEI DUBPTH0 DUBPTH1 DUBPTH2 DUBPTH3 LCI0 LCI1 LCI2 Configuration Register Upstream UTOPIA Backpressure Threshold Register 0 Upstream UTOPIA Backpressure Threshold Register 1 Upstream UTOPIA Backpressure Threshold Register 2 Upstream UTOPIA Backpressure Threshold Register 3 UTOPIA Backpressure Exceed Indication Register Downstream UTOPIA Backpressure Threshold Register 0 Downstream UTOPIA Backpressure Threshold Register 1 Downstream UTOPIA Backpressure Threshold Register 2 Downstream UTOPIA Backpressure Threshold Register 3 Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register LCI Transfer Register 0 LCI Transfer Register 1 LCI Transfer Register 2
147
R/W 181
Backpressure Control Registers FFFF R/W 181 FFFF R/W 183 FFFF R/W 184 FFFF R/W 185 0000 R/W 186
FFFF R/W 187 FFFF R/W 188 FFFF R/W 189 FFFF R/W 190 0080 0000 0000 0000 0000 0000 0000 0000 0000 R/W R/W R/W R/W R/W R -
LCI Table Transfer Registers R/W 192 R/W 193 R/W 194
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Data Sheet
ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000
See page
Register
Traffic Class Table Transfer Registers 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 TCT0 TCT1 TCT2 TCT3 QCT0 QCT1 QCT2 QCT3 QCT4 QCT5 QCT6 SBOC0 SBOC1 SBOC2 SBOC3 SBOC4 MGT0 MGT1 MGT2 TCT Transfer Register 0 TCT Transfer Register 1 TCT Transfer Register 2 TCT Transfer Register 3 R/W 198 R/W 201 R/W 204 R/W 207 R/W 213 R/W 214 R/W 217 R/W 219 R/W 220 R/W 221 R/W 222 R/W 225 R/W 226 R/W 227 R/W 228 R/W 229 R/W 232 R/W 233 R/W 234 R/W R/W R/W R/W -
Queue Configuration Table Transfer Registers Queue Configuration Transfer Register 0 0000 Queue Configuration Transfer Register 1 0000 Queue Configuration Transfer Register 2 0000 Queue Configuration Transfer Register 3 0000 Queue Configuration Transfer Register 4 0000 Queue Configuration Transfer Register 5 0000 Queue Configuration Transfer Register 6 0000 SBOC Transfer Register 0 SBOC Transfer Register 1 SBOC Transfer Register 2 SBOC Transfer Register 3 SBOC Transfer Register 4 MGT Transfer Register 0 MGT Transfer Register 1 MGT Transfer Register 2 Reserved Register Reserved Register Reserved Register Reserved Register 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Scheduler Block Occupancy Table Transfer Registers
Merge Group Table Transfer Registers
Mask Registers
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Register Description Table 7-2 Addr (hex) ABM-3G Registers Overview (cont'd) Description Reset P value (hex)
See page
Register
for Read/Write transfer access control of LCI-, Traffic Class-, Queue Configuration-, Scheduler Block Occupancy and Merge Group Tables 55/56 57/58 59/5A 5B 5C 5D 5E 5F 60/80 61/81 62/82 63/83 64/84 65/85 66/86 67/87 MASK0/ MASK1 MASK2/ MASK3 MASK4/ MASK5 MASK6 UCDV/ DCDV UQPTM0/ DQPTM0 UQPTM1/ DQPTM1 UQPTM2/ DQPTM2 Table Access Mask Registers 0/1 Table Access Mask Registers 2/3 Table Access Mask Registers 4/5 Table Access Mask Registers 6 Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register Upstream/Downstream Rate Shaper CDV Registers Reserved Register Reserved Register Upstream/Downstream Queue Parameter Table Mask Registers 0 Upstream/Downstream Queue Parameter Table Mask Registers 1 Upstream/Downstream Queue Parameter Table Mask Registers 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 R/W 235 R/W 236 R/W 237 R/W 238 R/W R/W R/W R/W R R -
Rate Shaper CDV Registers
R/W 239 R R -
Queue Parameter Table Mask Registers R/W 240 R/W 241 R/W 242
Data Sheet
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Register Description Table 7-2 Addr (hex) 68/88 69/89 6A/8A ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000
See page
Register
UQPTM3/ DQPTM3 UQPTM4/ DQPTM4 UQPTM5/ DQPTM5 USCONF/ DSCONF UQPT1T0/ DQPT1T0 UQPT1T1/ DQPT1T1 UQPT2T0/ DQPT2T0 UQPT2T1/ DQPT2T1 UQPT2T2/ DQPT2T2 UQPT2T3/ DQPT2T3 -
Upstream/Downstream Queue Parameter Table Mask Registers 3 Upstream/Downstream Queue Parameter Table Mask Registers 4 Upstream/Downstream Queue Parameter Table Mask Registers 5 Upstream/Downstream Scheduler Configuration Registers Reserved Register Reserved Register Reserved Register Reserved Register Upstream/Downstream QPT1 Table Transfer Register 0 Upstream/Downstream QPT1 Table Transfer Register 1 Upstream/Downstream QPT2 Table Transfer Register 0 Upstream/Downstream QPT2 Table Transfer Register 1 Upstream/Downstream QPT2 Table Transfer Register 2 Upstream/Downstream QPT2 Table Transfer Register 3 Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register
150
R/W 243 R/W 244 R/W 245
Scheduler Configuration Register 6B/8B 6C/8C 6D/8D 6E/8E 6F/8F 70/90 71/91 72/92 73/93 74/94 75/95 76/96 77/97 78/98 79/99 7A/9A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 R/W 246 R R R R -
Queue Parameter Table Transfer Registers R/W 249 R/W 250 R/W 253 R/W 254 R/W 255 R/W 256 R/W R/W R/W R/W R/W 2001-12-17
Data Sheet
ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) 7B/9B 7C/9C 7D/9D 7E/9E 7F/9F ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000 0000
See page
Register
-
Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register
R/W R/W R/W R/W R/W -
Scheduler Block Configuration Table Transfer/Mask Registers SDRAM Refresh Registers UTOPIA Port Select of Common Real Time Queue Registers A0/B8 A1/B9 A2/BA A3/BB A4/BC USADR/ DSADR USCTI/ DSCTI UECRI/ DECRI UECRF/ DECRF UCRTQ/ DCRTQ USCTFM/ DSCTFM USCTFT/ DSCTFT USCEN0/ DSCEN0 USCEN1/ DSCEN1 USCEN2/ DSCEN2 USCEN3/ DSCEN3 Upstream/Downstream SCTI Address Registers Upstream/Downstream SCTI Transfer Registers Upstream/Downstream Empty Cycle Rate Integer Part Registers Upstream/Downstream Empty Cycle Rate Fractional Part Registers Upstream/Downstream Common Real Time Queue UTOPIA Port Select Registers Upstream/Downstream SCTF Mask Registers Upstream/Downstream SCTF Transfer Registers Reserved Register Upstream/Downstream Scheduler Block Enable 0 Registers Upstream/Downstream Scheduler Block Enable 1 Registers Upstream/Downstream Scheduler Block Enable 2 Registers Upstream/Downstream Scheduler Block Enable 3 Registers
151
0000 0000 0000 0000 0000
R/W 259 R/W 260 R/W 263 R/W 264 R/W 265
A5/BD A6/BE A7/BF A8/C0 A9/C1 AA/C2 AB/C3
0000 0000 0000 0000 0000 0000 0000
R/W 266 R/W 269 R -
Scheduler Block Enable Registers R/W 270 R/W 271 R/W 272 R/W 273
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) AC/C4 AD/C5 AE/C6 AF/C7 ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000
See page
Register
USCEN4/ DSCEN4 USCEN5/ DSCEN5 USCEN6/ DSCEN6 USCEN7/ DSCEN7 UCRTRI/ DCRTRI UCRTRF/ DCRTRF ERCT0 ERCT1 ERCM0 ERCM1 -
Upstream/Downstream Scheduler Block Enable 4 Registers Upstream/Downstream Scheduler Block Enable 5 Registers Upstream/Downstream Scheduler Block Enable 6 Registers Upstream/Downstream Scheduler Block Enable 7 Registers Upstream/Downstream CRT Rate Integer Registers Upstream/Downstream CRT Rate Fractional Registers Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register AVT Table Transfer Register 0 AVT Table Transfer Register 1 AVT Table Access Mask Register 0 AVT Table Access Mask Register 1 Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register Reserved Register
152
R/W 274 R/W 275 R/W 276 R/W 277
Common Real Time Queue Rate Registers B0/C8 B1/C9 B2 B3 B4 B5 B6 B7 CA CB CC CD CE CF D0 D1 D2 D3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 R/W 278 R/W 279 R R R R R R -
AVT Table Registers R/W 282 R/W 283 R/W 284 R/W 285 R R R R R R -
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) D4 D5 D6 D7 D8 D9 DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 R R
See page
Register
ERCCONF0 PLL1CONF PLLTST EXTRAMD0 EXTRAMD1 EXTRAMA0 EXTRAMA1 EXTRAMC VERL VERH ISRU ISRD ISRC IMRU IMRD IMRC -
Reserved Register ERC Configuration Register 0 Reserved Register PLL1 Configuration Register Reserved Register PLL Test Register External RAM Test Data Register 0 External RAM Test Data Register 1 External RAM Test Address Register Low External RAM Test Address Register High External RAM Test Command Register Version Number Low Register Version Number High Register Interrupt Status Register Upstream Interrupt Status Register Downstream Interrupt Status Register Common Interrupt Mask Register Upstream Interrupt Mask Register Downstream Interrupt Mask Register Common Reserved Register Reserved Register
-
R/W 286
PLL Control Registers R/W 287 R R/W 289 R/W 290 R/W 291 R/W 292 R/W 293 R/W 294 295 296
External RAM Test Registers
ABM-3G Version Code Registers F083 R 1007 0000 0000 0000 0000 0000 0000 0000 0000 R
Interrupt Status/Mask Registers R/W 297 R/W 300 R/W 303 R/W 304 R/W 305 R/W 306 R R -
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000
See page
Register
RAM Select Registers EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA MAR WAR USTATUS MODE1 MODE2 UTRXCFG UUTRXP0 UUTRXP1 UUTRXP2 DUTRXP0 DUTRXP1 DUTRXP2 UUTTXCFG DUTTXCFG UUTTXP0 UUTTXP1 Memory Address Register Word Address Register ABM-3G UTOPIA Status Register ABM-3G Mode 1 Register ABM-3G Mode 2 Register Upstream/Downstream UTOPIA Receive Configuration Register Upstream UTOPIA Receive Port Register 0 Upstream UTOPIA Receive Port Register 1 Upstream UTOPIA Receive Port Register 2 Downstream UTOPIA Receive Port Register 0 Downstream UTOPIA Receive Port Register 1 Downstream UTOPIA Receive Port Register 2 Upstream UTOPIA Transmit Configuration Register Downstream UTOPIA Transmit Configuration Register Upstream UTOPIA Transmit Port Register 0 Upstream UTOPIA Transmit Port Register 1 R/W 307 R/W 309 R/W 311 R/W 312 R/W 315 R/W 317 R/W 319 R/W 320 R/W 321 R/W 322 R/W 323 R/W 324 R/W 325 R/W 327 R/W 329 R/W 330
Global ABM-3G Status and Mode Registers
UTOPIA Configuration Registers
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Table 7-2 Addr (hex) FB FC FD FE ABM-3G Registers Overview (cont'd) Description Reset P value (hex) 0000 0000 0000 0000
See page
Register
UUTTXP2 DUTTXP0 DUTTXD1 DUTTXD2
Upstream UTOPIA Transmit Port Register 2 Downstream UTOPIA Transmit Port Register 0 Downstream UTOPIA Transmit Port Register 1 Downstream UTOPIA Transmit Port Register 2 TEST Register
R/W 331 R/W 332 R/W 333 R/W 334
Test Registers/Special Mode Registers FF TEST 0000 R/W 335
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description
7.2 7.2.1
Register 1
Detailed Register Descriptions Cell Flow Test Registers
UCFTST/DCFTST Upstream/Downstream Cell Flow Test Registers
CPU Accessibility: Reset Value: Offset Address: Typical Usage:
Read/Write 0000 H UCFTST 01H DCFTST 11H Written by CPU to test internal integrity functions during special system test scenarios 14 13 12 11 10 9 8
Bit
15
Unused(15:8) Bit 7 6 5 4 3 2 1 0
Unused(7:2)
*
TSTBIP TSTQID
TSTBIP
Test BIP-8 Supervision 0 Normal Operation: BIP-8 for cell protection is generated normally. No 'BIP8ER' interrupt should occur indicating a cell storage failure. Test Mode: Least Significant Bit (LSB) of BIP-8 is inverted to test BIP-8 checking function. A 'BIP8ER' (Register 101: ISRU, Register 102: ISRD) interrupt is generated whenever a cell is Read out of the Cell Buffer RAM.
1
TSTQID
Test Queue ID Supervision (see "Cell Queue Supervision" on Page 90) 0 Normal Operation: A correct QID is generated. No 'BUFER4' interrupt should occur indicating an internal queue pointer failure.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description 1 Test Mode: The LSB of the QID is inverted to test the QID checking function. A 'BUFER4' (Register 101: ISRU, Register 102: ISRD) interrupt is generated whenever a cell is Read out from the Cell Buffer RAM.
Note: The respective QID value is stored with each cell when written to the appropriate queue in the cell storage RAM. The ABM-3G checks the stored QID value against the supposed QID when a cell is read back from the cell storage RAM.
7.2.2
Register 2
SDRAM Configuration Registers
URCFG/DRCFG Upstream/Downstream SDRAM Configuration Registers
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15
Read/Write 0033 H URCFG (Reserved) 14 13 12 11 10 9 8 02H DRCFG 12H
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0)
*
Note: These registers are for internal use only. Do not to Write a value different from the Reset Value 0033H to Registers URCFG/DRCFG.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description
7.2.3
Register 3
Cell Insertion/Extraction and AAL5 Control Registers
UA5TXHD0/DA5TXHD0 Upstream/Downstream AAL5 Transmit Header 0 Registers
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15
Read/Write 0000 H UA5TXHD0 05H DA5TXHD0 15H Written by CPU 14 13 12 11 10 9 8
LCI(11:4), VPI(11:4) or GFC(3:0) | VPI(7:4), LCI(11:4), VPI(11:4) or GFC(3:0) | VPI(7:4), Bit 7 6 5 LCI(3:0), VPI(3:0), LCI(3:0), VPI(3:0)
*
4
3
2
1
0
VCI(15:12), LCI(15:12), VCI(15:12), VCI(15:12)
First 16-bit word of an ATM cell. The ABM-3G does not interpret these bit fields, but copies them into ATM cells that are inserted during AAL5 packet segmentation process. Inserted cells are forwarded to the ABM-3G like any cell received by the respective UTOPIA Interface. Thus the bit field usage must comply to the selected LCI mapping mode in the particular application. VPI(11:0) or GFC(3:0) | VPI(7:0) or LCI(11:0) The meaning of this bit field depends on the selected LCI mapping mode in Register 110: MODE1: MODE1->LCIMOD(1:0): '00' '01' VPI Address translated mode: LCI(11:0) VPI transparent mode: * NNI cell format: 12-bit VPI field * UNI cell format: 4-bit GFC field and 8-bit VPI field VPI Address translated mode: LCI(11:0) VPI transparent mode: * NNI cell format: 12-bit VPI field * UNI cell format: 4-bit GFC field and 8 bit VPI field
158 2001-12-17
'10' '11'
Data Sheet
ABM-3G PXF 4333 V1.1
Register Description Note: If LCI mapping mode '10' is chosen LCI(13:12) cannot be specified, i.e. AAL5 cell insertion is limited to the LCI range 0..4095. VCI(15:12) or LCI(15:12) or VCI(15:12) The meaning of this bit field depends on the selected LCI mapping mode in Register 110: MODE1: MODE1->LCIMOD(1:0): '00' '01' '10' '11' VCI transparent mode: VCI(15:12) VCI Address translated mode: LCI(15:12) VCI transparent mode: VCI(15:12) VCI transparent mode: VCI(15:12)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 4 UA5TXHD1/DA5TXHD1 Upstream/Downstream AAL5Transmit Header 1 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5TXHD1 06H DA5TXHD1 16H Written by CPU 14 13 12 11 10 9 8
VCI(11:4), LCI(11:4), VCI(11:4), VCI(11:4) Bit 7 6 5 4 3 2 PT(2:0) CLP 1 0
VCI(3:0), LCI(3:0), VCI(3:0), VCI(3:0)
*
Second 16-bit word of an ATM cell. The ABM-3G does not interpret these bit fields, but copies them into ATM cells that are inserted during AAL5 packet segmentation process. Inserted cells are forwarded to the ABM-3G like any cell received by the respective UTOPIA Interface. Thus the bit field usage must comply to the selected LCI mapping mode in the particular application. VCI(11:0) or LCI(11:0) The meaning of this bit field depends on the selected LCI mapping mode in Register 110: MODE1: MODE1->LCIMOD(1:0): '00' '01' '10' '11' PT(2:0) VCI transparent mode: VCI(11:0) VCI Address translated mode: LCI(11:0) VCI transparent mode: VCI(11:0) VCI transparent mode: VCI(11:0)
Payload Type Field in ATM cell Header
Data Sheet
160
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ABM-3G PXF 4333 V1.1
Register Description PT(0) is automatically handled by the ABM-3G (End of Packet indication set to '1' in last cell of any AAL5 segmented packet). PT(1) ('Congestion Experienced') may be overwritten by CPU anytime during segmentation process and will be inserted in the following AAL5 cell generated. This field must be initialized to all 0s. CLP Cell Loss Priority Bit in ATM cell Header The CLP bit is copied transparently and may be overwritten (changed) by CPU anytime during segmentation process (new value will be inserted in the following AAL5 cell generated).
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 5 UA5TXDAT0/DA5TXDAT0 Upstream/Downstream AAL5Transmit Data 0 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5TXDAT 0 07H DA5TXDAT0 17H
Written by CPU 14 13 12 11 10 9 8
Octet(4n)(7:0) Bit 7 6 5 4 3 2 1 0
Octet(4n+1)(7:0)
*
Cell Transmit Data Transfer Register Octet(4n)(7:0) Octet(4n+1)(7:0) Payload data Octet (4n) Payload data Octet (4n+1) The payload data octets of a cell to be inserted in either upstream or downstream direction are written by consecutive write accesses to registers UTXDAT0/DTXDAT0 and UTXDAT1/DTXDAT1 in alternating manner until end of packet: cycle n=0: Octet 0 and 1: write to UTXDAT0/DTXDAT0 cycle n=0: Octet 2 and 3: write to UTXDAT1/DTXDAT1 cycle n=1: Octet 4 and 5: write to UTXDAT0/DTXDAT0 cycle n=1: Octet 6 and 7: write to UTXDAT1/DTXDAT1 ...
Data Sheet
162
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ABM-3G PXF 4333 V1.1
Register Description Register 6 UA5TXDAT1/DA5TXDAT1 Upstream/Downstream AAL5 Transmit Data 1 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5TXDAT1 08H Written by CPU 14 13 12 11 10 9 8 DA5TXDAT1 18H
Octet(4n+2)(7:0) Bit 7 6 5 4 3 2 1 0
Octet(4n+3)(7:0)
Cell Transmit Data Transfer Register Octet(4n+2)(7:0) Octet(4n+3)(7:0) Payload data Octet (4n+2) Payload data Octet (4n+3) The payload data octets of a cell to be inserted in either upstream or downstream direction are written by consecutive write accesses to registers UTXDAT0/DTXDAT0 and UTXDAT1/DTXDAT1 in alternating manner until end of packet: cycle n=0: Octet 0 and 1: write to UTXDAT0/DTXDAT0 cycle n=0: Octet 2 and 3: write to UTXDAT1/DTXDAT1 cycle n=1: Octet 4 and 5: write to UTXDAT0/DTXDAT0 cycle n=1: Octet 6 and 7: write to UTXDAT1/DTXDAT1 ...
Data Sheet
163
2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Register 7 UA5TXTR/DA5TXTR Upstream/Downstream AAL5 Transmit Trailer Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5TXTR 09H DA5TXTR 19H Written by CPU 14 13 12 11 10 9 8
CPCSUU(7:0) Bit 7 6 5 4 CPI(7:0) 3 2 1 0
CPCS-UU(7:0)
Common Part Convergence Sublayer User to User Indication The CPCS-UU bit field is copied transparently into the CPCS-PDU trailer in the last cell of an AAL5 segmented packet.
CPI(7:0)
Common Part Indication The CPI bit field is copied transparently into the CPCS-PDU trailer in the last cell of an AAL5 segmented packet.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 8
*
UA5TXCMD/DA5TXCMD Upstream/Downstream AAL5 Transmit Command Registers
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 AAL5EN Bit 7 6
Read/Write 0000 H UA5TXCMD 0AH DA5TXCMD 1AH Written by CPU (write only, read always returns 0000) 14 13 12 11 PLENGTH(14:8) 5 4 3 2 1 0 10 9 8
PLENGTH(7:0)
*
AAL5EN
AAL5 Segmentation Enable This bit enables AAL5 segmentation process accompanied by the payload length octet counter PLENGTH: '0' AAL5 segmentation is disabled. Payload data octets written to the cell transmit data registers are ignored. Note: Setting AAL5EN='0' during an active packet segmentation process leads to an abort of the packet, i.e. the current cell is inserted with PT(0)='1' (End of Packet indication) and CPCSSDU Length field of the trailer set to 0. To abort it is recommended to write all 0 to the register: AAL5EN | PLENGTH(14:0) = 0000H '1' AAL5 segmentation is enabled. Payload data octets written to the cell transmit data registers are processed and the CPCS-PDU trailer is automatically appended in the last cell controlled by the payload length octet counter.
PLENGTH(14:0)
Payload Length Octet Counter This bit field represents the number of PDU payload octets for the current packet and is equal to the CPCS-SDU length field which is automatically inserted in the PDU trailer (last cell of the packet). The ABM-3G uses this counter value to control the AAL5 segmentation process. Note: The maximum supported CPCS-SDU length is 32767 octets.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 9 UA5RXHD0/DA5RXHD0 Upstream/Downstream AAL5 Receive Header 0 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5RXHD0 0BH Read by CPU 14 13 12 11 10 9 8 DA5RXHD0 1BH
LCI(11:4), VPI(11:4) or GFC(3:0) | VPI(7:4), LCI(11:4), VPI(11:4) or GFC(3:0) | VPI(7:4), Bit 7 6 5 LCI(3:0), VPI(3:0), LCI(3:0), VPI(3:0) 4 3 2 1 0
VCI(15:12), LCI(15:12), VCI(15:12), VCI(15:12)
Header octets one and two of first ATM cell of packet. The ABM-3G SAR unit does not interpret these bit fields, but copies them from ATM cells that are extracted during AAL5 packet reassembly process. Extracted cells are forwarded from the ABM-3G like any cell to be transmitted by the respective UTOPIA Interface. Thus, the bit field usage depends on the selected LCI mapping mode in the particular application. From scheduler point of view the reassembly unit is addressed as UTOPIA port number 30H.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description VPI(11:0) or GFC(3:0) | VPI(7:0) or LCI(11:0) The meaning of this bit field depends on the selected LCI mapping mode in Register 110: MODE1: MODE1->LCIMOD(1:0): '00' '01' VPI Address translated mode: LCI(11:0) VPI transparent mode: * NNI cell format: 12 bit VPI field * UNI cell format: 4 bit GFC field and 8 bit VPI field VPI Address translated mode: LCI(11:0) VPI transparent mode: * NNI cell format: 12 bit VPI field * UNI cell format: 4 bit GFC field and 8 bit VPI field
'10' '11'
Note: If LCI mapping mode '10' is chosen LCI(13:12) are not given to the user. VCI(15:12) or LCI(15:12) or VCI(15:12) The meaning of this bit field depends on the selected LCI mapping mode in Register 110: MODE1: MODE1->LCIMOD(1:0): '00' '01' '10' '11' VCI transparent mode: VCI(15:12) VCI Address translated mode: LCI(15:12) VCI transparent mode: VCI(15:12) VCI transparent mode: VCI(15:12)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 10 UA5RXHD1/DA5RXHD1 Upstream/Downstream AAL5 Receive Header 1 Registers
*
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15
Read/Write 0000 H UA5RXHD1 0CH Read by CPU 14 13 12 11 10 9 8 DA5RXHD1 1CH
VCI(11:4), LCI(11:4), VCI(11:4), VCI(11:4) Bit 7 6 5 4 3 2 PT(2:0) CLP 1 0
VCI(3:0), LCI(3:0), VCI(3:0), VCI(3:0)
*
Header octets three and four of first ATM cell of AAL5 packet. The ABM-3G SAR unit does not interpret these bit fields, but copies them from ATM cells that are extracted during AAL5 packet reassembly process. Extracted cells are forwarded from the ABM-3G like any cell to be transmitted by the respective UTOPIA Interface. Thus, the bit field usage depends on the selected LCI mapping mode in the particular application. From scheduler point of view the reassembly unit is addressed as UTOPIA port number 30H. VCI(11:0) or LCI(11:0) The meaning of this bit field depends on the selected LCI mapping mode in Register 110: MODE1: MODE1->LCIMOD(1:0): '00' '01' '10' '11' VCI transparent mode: VCI(11:0) VCI Address translated mode: LCI(11:0) VCI transparent mode: VCI(11:0) VCI transparent mode: VCI(11:0)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description PT(2:0) Payload Type Field in ATM cell Header PT(0) is automatically handled by the ABM-3G (End of Packet detection). Note: OAM or RM cells detected with PT(2)='1' are discarded by the reassembly unit and ignored for the packet reassembly process. Thus packet reassembly is not disturbed by inserted OAM cells. CLP Cell Loss Priority Bit in ATM cell Header The CLP bit is copied transparently from the ATM cell.
Data Sheet
169
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ABM-3G PXF 4333 V1.1
Register Description Register 11 UA5RXDAT0/DA5RXDAT0 Upstream/Downstream AAL5 Receive Data 0 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5RXDAT0 0D H Read by CPU 14 13 12 11 10 9 8 DA5RXDAT0 1DH
Octet(4n)(7:0) Bit 7 6 5 4 3 2 1 0
Octet(4n+1)(7:0)
Cell Receive Data Transfer Register Octet(4n)(7:0) Octet(4n+1)(7:0) Payload data Octet (4n) Payload data Octet (4n+1) The payload data octets of a cell extracted from either upstream or downstream direction are read by consecutive read accesses to registers URXDAT0/DRXDAT0 and URXDAT1/DRXDAT1 in alternating manner until end of packet: cycle n=0: Octet 0 and 1: read from URXDAT0/DRXDAT0 cycle n=0: Octet 2 and 3: read from URXDAT1/DRXDAT1 cycle n=1: Octet 4 and 5: read from URXDAT0/DRXDAT0 cycle n=1: Octet 6 and 7: read from URXDAT1/DRXDAT1 ... After EOP is found, CPCS-UU, CPI and Status is read.
Data Sheet
170
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ABM-3G PXF 4333 V1.1
Register Description Register 12 UA5RXDAT1/DA5RXDAT1 Upstream/Downstream AAL5 Receive Data 1 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UA5RXDAT1 0EH Read by CPU 14 13 12 11 10 9 8 DA5RXDAT1 1EH
Octet(4n+2)(7:0) Bit 7 6 5 4 3 2 1 0
Octet(4n+3)(7:0)
Cell Receive Data Transfer Register Octet(4n)(7:0) Octet(4n+1)(7:0) Payload data Octet (4n) Payload data Octet (4n+1) The payload data octets of a cell extracted from either upstream or downstream direction are read by consecutive read accesses to registers URXDAT0/DRXDAT0 and URXDAT1/DRXDAT1 in alternating manner until end of packet: cycle n=0: Octet 0 and 1: read from URXDAT0/DRXDAT0 cycle n=0: Octet 2 and 3: read from URXDAT1/DRXDAT1 cycle n=1: Octet 4 and 5: read from URXDAT0/DRXDAT0 cycle n=1: Octet 6 and 7: read from URXDAT1/DRXDAT1 ... After EOP is found, CPCS-UU, CPI and Status is read.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 13 UA5SARS/DA5SARS Upstream/Downstream AAL5 SAR Status Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 PE Read/Write 0080H UA5SARS 0FH DA5SARS 1FH Read and written by CPU 14 CRC ERR 6 SP 13 ILEN 12 MFLE 11 RAB 10 OV(1:0) 9 8 RXS
Bit
7 WAIT
5 SAB
4 SE
3
2
1
0
unused(3:0)
PE
Packet End A `1' indicates that with the preceding read to register UA5RXDAT0/ DA5RXDAT0 or UA5RXDAT1/DA5RXDAT1, the last two bytes of the current packet have been read.
CRCERR ILEN
CRC Error A `1' indicates that the CRC32 of the current packet is erroneous. Illegal Length A `1' indicates that the length of the current packet is erroneous, i.e the number of octets does not match the length field in the AAL5 trailer or exceeds the maximum supported packet length of 65536 octets.
MFLE
Maximum Frame Length Exceeded A `1' indicates that the length of the current packet exceeds the maximum supported packet length of 65536 octets.
RAB
Receive Abort A `1' indicates that the length field of the current packet is 0, indicating an aborted or corrupted packet.
OV(1:0)
Octets Valid This bit field indicates the number of valid octets in registers UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and DA5RXDAT1 respectively.
Data Sheet
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Register Description RXS Receive Packet Start A `1' indicates that the first octets of a new packet are available in registers UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and DA5RXDAT1 respectively. WAIT Wait A `1' indicates that no valid octets are available in registers UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and DA5RXDAT1 respectively. Read access to any read register while WAIT is asserted results into an error interrupt. SP Segmentation Pending A `1' indicates that a cell is ready to be transmitted towards the ABM-3G core. A cell is ready either when 48 octets have been written to UA5TXDAT0 and UA5TXDAT1 or DA5TXDAT0 and DA5TXDAT1 respectively or when the last cell is being built. Bit `SP' is set when the 48-byte transmit buffer is full and it is reset as soon as at least 4-octet space is available for new octets. The microprocessor has to poll this bit before writing the next 48-octet bunch or beginning a new packet. If the microprocessor attempts to write to UA5TXDAT0 and UA5TXDAT1 or DA5TXDAT0 and DA5TXDAT1 respectively while `SP' is set, an interrupt is generated and the write access is delayed by the READY signal. SAB Segmentation Abort A `1' indicates that the transmission of a packet has been aborted because the enable bit EN was reset by the microprocessor before the transmission was completed. The AAL5 unit automatically closed the packet with an abort sequence in the last cell (length field set to 0). Note: Status bit `SE' is not set in this case. SE Segmentation Ended A `1' indicates that the transmission of a packet has been completed successfully. Note: Status bits SP, SAB, SE are used for transmit, the others for receive.
Data Sheet
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Register Description
7.2.4
Buffer Occupation Counter Registers
Register 14 UBufferOcc/DBufferOcc Upstream/Downstream Buffer Occupation Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read only 0000 H UBufferOcc 20H Read by CPU 14 13 12 11 10 9 8 DBufferOcc 21H
UBufferOcc/DBufferOcc(17:10) Bit 7 6 5 4 3 2 1 0
UBufferOcc/DBufferOcc(9:2)
UBufferOcc(17:2) DBufferOcc(17:2)
Upstream Buffer Occupation Counter Downstream Buffer Occupation Counter These bit fields represent the most significant 16 bits of the internal 18-bit wide counters reflecting the number of cells currently stored in the upstream/downstream cell storage RAM. The CPU determines the buffer fill level with a granularity of 4 by reading register UBufferOcc/DBufferOcc and left shifting the value by 2: fill_level(17:0):= (xBufferOcc(17:2) << 2)
Data Sheet
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Register Description Register 15 UBufferOccNg/DBufferOccNg Up-/Downstream Non-Guaranteed Buffer Occupation Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read only 0000 H UBufferOccNg Read by CPU 14 13 12 11 10 9 8 22 H DBufferOccNg 23H
UBufferOccNg/DBufferOccNg(17:10) Bit 7 6 5 4 3 2 1 0
UBufferOccNg/DBufferOccNg(9:2)
*
UBufferOccNg(17:2) Upstream Non-Guaranteed Buffer Occupation Counter DBufferOccNg(17:2) Downstream Non-Guaranteed Buffer Occupation Counter These bit fields represent the most significant 16 bits of the internal 18-bit wide counters reflecting the number of nonguaranteed cells currently stored in the upstream/downstream cell storage RAM. The CPU determines the number of cells with a granularity of 4 by reading register UBufferOccNg/DBufferOccNg and left shifting the value by 2: fill_level(17:0):= (xBufferOccNg(17:2) << 2) "Non-Guaranteed" cell count refers to cells, that are accepted (stored) because of shared buffer availability although the guaranteed minimum per queue buffer size is already occupied by the specific queue. The sum of all per queue guaranteed buffer sizes virtually divides the global buffer space into a "guaranteed" part and a "non-guaranteed" (shared) part. Note: This counter function has been modified from ABM v1.1 since minimum per queue buffer reservation was introduced in ABM-3G v1.1. In ABM v1.1 these counters represented the number stored "non-real-time" cells belonging to traffic classes with the real-time indication bit 'RTind' cleared in the traffic class table.
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Register Description
7.2.5
Buffer Threshold and Occupation Capture Registers
Register 16 UBufMax/DBufMax Upstream/Downstream Buffer Maximum Threshold Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UBufMax 24H DBufMax 25H Written by CPU 14 13 12 11 10 9 8
UBufMax/DBufMax(17:10) Bit 7 6 5 4 3 2 1 0
UBufMax/DBufMax(9:2) UBufMax(17:2) DBufMax(17:2) Upstream Buffer Maximum Threshold Downstream Buffer Maximum Threshold These bit fields determine a maximum limit for the total upstream and downstream buffer size with a granularity of 4 cells. The values depend on: * The size of the external cell pointer RAM, * Whether the downstream cell storage RAM is connected. See Table 7-3 for recommended values. The CPU programs the maximum number of cells with a granularity of 4 by right shifting the value by 2: xBufMax(17:2):= (maximum_cells(17:0) >> 2) Table 7-3 provides typical values and related RAM sizes:
Data Sheet
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Register Description
*
Table 7-3 Cell Pointer SSRAM
External RAM Sizes Min. Required Upstream Cell SDRAM UBufMax UpMin. stream Required Buffer Downstream Cell SDRAM 3FFFFH DBufMax Downstream Buffer
e.g. 512 k x 32 bit e.g. 256 k x 32 bit e.g. 128 k x 32 bit e.g. 256 k x 32 bit e.g. 128 k x 32 bit e.g. 64 k x 32 bit
128 Mb 128 Mb e.g. e.g. 2*(4Mb*16) 2*(4Mb*16) 64 Mb 64 Mb e.g. e.g. 1*(2Mb*32) 1*(2Mb*32) 32 Mb 32 Mb
256k cells 3FFFFH
256k cells
1FFFFH
128k cells 1FFFFH
128k cells
0FFFFH
64k cells
0FFFFH
64k cells
none 128 Mb e.g. 2*(4Mb*16) none 64 Mb e.g. 1*(2Mb*32) 32 Mb none
3FFFFH
256k cells 00000H
0
1FFFFH
128k cells 00000H
0
0FFFFH
64k cells
00000H
0
Note: The upstream cell storage RAM must always be connected. Note: The size of the cell storage RAMs need not to be specified. Its minimum size is determined by the setting of UBufMax/DbufMax.
Data Sheet
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Register Description Register 17 UMAC/DMAC Upstream/Downstream Maximum Occupation Capture Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read only, self-clearing on Read 0000 H UMAC Read by CPU 14 13 12 11 10 9 8 26H DMAC 27H
UMAC/DMAC(17:10) Bit 7 6 5 4 3 2 1 0
UMAC/DMAC(9:2) UMAC(17:2) DMAC(17:2) Upstream Maximum Occupation Capture Counter Downstream Maximum Occupation Capture Counter These bit fields represent the most significant 16 bits of the internal 18-bit wide counters reflecting the absolute maximum number of cells stored in the respective external cell buffer since the last Read access (peak cell filling level within measurement interval). The CPU determines the maximum number of cells with a granularity of 4 by reading register UMAC/DMAC and left shifting the value by 2: max_level(17:0):= (xMAC(17:2) << 2) The counter value is automatically cleared to 0000H after Read.
Data Sheet
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Register Description Register 18 UMIC/DMIC Upstream/Downstream Minimum Occupation Capture Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read only, self-clearing on Read FFFF H (modified by chip logic immediately after reset) UMIC Read by CPU 14 13 12 11 10 9 8 28H DMIC 29H
UMIC/DMIC(17:10) Bit 7 6 5 4 3 2 1 0
UMIC/DMIC(9:2) UMIC(17:2) DMIC(17:2) Upstream Minimum Occupation Capture Counter Downstream Minimum Occupation Capture Counter These bit fields represent the most significant 16 bits of the internal 18-bit wide counters reflecting the absolute minimum number of cells stored in the respective external cell buffer since the last Read access (minimum cell filling level within measurement interval). The CPU determines the minimum number of cells with a granularity of 4 by reading register UMIC/DMIC and left shifting the value by 2: min_level(17:0):= (xMIC(17:2) << 2) The counter value is automatically cleared to 0000H after Read. Note: The reset value is modified by chip logic immediately after reset or clearing read and thus shall not be included in register reset value test programs.
Data Sheet
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Register Description Register 19 CLP1DIS CLP1 Discard Global Threshold Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H CLP1DIS 2AH Written by CPU 14 13 12 11 10 9 8
DCLP1DIS(13:6) Bit 7 6 5 4 3 2 1 0
UCLP1DIS(13:6) UCLP1DIS(13:6) DCLP1DIS(13:6) Upstream CLP1 Discard Threshold value Downstream CLP1 Discard Threshold value These 8-bit values determine a global 14-bit threshold value (granularity of 64 cells) that enables discard of low-priority (CLP='1') cells. The threshold values are compared with the per scheduler low priority cell counter SBOccLP (Scheduler Block Low Priority Occupancy) (see Internal Table 4: Scheduler Block Occupancy Table Transfer Registers SBOC0..SBOC4) and enables all CLP1 related discard thresholds, i.e.: TCT1.BufCiCLP1(7:0) (Register 34: TCT1) TCT2.SBCiCLP1(7:0) (Register 35: TCT2) TCT0.QueueCiCLP1(11:0) (Register 33: TCT0) As a second condition, CLP1 related discard thresholds are only effective, if the specific queue that is asked to accept the cell is associated to a traffic class that has EPD function disabled (EPDen='0', see "Traffic Class Table Transfer Registers TCT0, TCT1, TCT2, TCT3" on Page 195). The CPU programs the threshold with a granularity of 64 cells by right shifting the value by 6: xCLP1DIS(13:6):= (threshold_value(13:0) >> 6)
Data Sheet
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Register Description
7.2.6
Configuration Register
Register 20 CONFIG Configuration Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write 0000 H 2B H Written by CPU 13 12 11 10 9 8
Unused(13:6) Bit 7 6 5 4 3 2 1 0
Unused(5:0)
Reserved1 Unused
Reserved1
this bit is for internal use only and must be set to 0 during normal operation.
7.2.7
Backpressure Control Registers
Register 21 UUBPTH0 Upstream UTOPIA Backpressure Threshold Register 0
*
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14
Read/Write FFFF H UUBPTH0 Written by CPU 13 12 11 10 9 8 2CH
UUBPTH0(17:10)
Data Sheet
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Register Description
Bit
*
7
6
5
4
3
2
1
0
UUBPTH0(9:2) UUBPTH0(17:2) Upstream UTOPIA Backpressure Threshold 0 This bit field determines the backpressure threshold for the Upstream UTOPIA Receive Interface Group 0 (see Chapter 5.1.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: UUBPTH0(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 22 UUBPTH1 Upstream UTOPIA Backpressure Threshold Register 1
*
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14
Read/Write FFFF H UUBPTH1 Written by CPU 13 12 11 10 9 8 2DH
UUBPTH1(17:10) Bit 7 6 5 4 3 2 1 0
UUBPTH1(9:2)
*
UUBPTH1(17:2)
Upstream UTOPIA Backpressure Threshold 1 This bit field determines the backpressure threshold for the Upstream UTOPIA Receive Interface Group 1 (see Chapter 5.1.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: UUBPTH1(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 23 UUBPTH2 Upstream UTOPIA Backpressure Threshold Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write FFFF H UUBPTH2 2EH Written by CPU 13 12 11 10 9 8
UUBPTH2(17:10) Bit 7 6 5 4 3 2 1 0
UUBPTH2(9:2)
UUBPTH2(17:2)
Upstream UTOPIA Backpressure Threshold 2 This bit field determines the backpressure threshold for the Upstream UTOPIA Receive Interface Group 2 (see Chapter 5.1.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: UUBPTH2(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 24 UUBPTH3 Upstream UTOPIA Backpressure Threshold Register 3 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write FFFF H UUBPTH3 2EH Written by CPU 13 12 11 10 9 8
UUBPTH3(17:10) Bit 7 6 5 4 3 2 1 0
UUBPTH3(9:2)
UUBPTH3(17:2)
Upstream UTOPIA Backpressure Threshold 3 This bit field determines the backpressure threshold for the Upstream UTOPIA Receive Interface Group 3 (see Chapter 5.1.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: UUBPTH3(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 25 UBPEI UTOPIA Backpressure Exceed Indication Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write 0000 H UBPEI Read by CPU 13 12 11 10 9 8 30H
Unused(7:0) Bit 7 6 5 4 3 2 1 0
DUBPEI(3:0)
UUBPEI(3:0)
DUBPEI(3:0) UUBPEI(3:0)
Downstream UTOPIA Backpressure Exceed Indication (3:0) Upstream UTOPIA Backpressure Exceed Indication (3:0) These bits indicate the respective UTOPIA backpressure threshold status. Bit i (i = 0..3) active indicates, that the backpressure threshold for group i is exceeded (bit = `H') and the UTOPIA Receive Interface backpressures the respective UTOPIA ports.
Data Sheet
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Register Description Register 26 DUBPTH0 Downstream UTOPIA Backpressure Threshold Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write FFFF H DUBPTH0 31H Written by CPU 13 12 11 10 9 8
DUBPTH0(17:10) Bit 7 6 5 4 3 2 1 0
DUBPTH0(9:2)
DUBPTH0(17:2)
Downstream UTOPIA Backpressure Threshold 0 This bit field determines the backpressure threshold for the Downstream UTOPIA Receive Interface Group 0 (see Chapter 5.2.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: DUBPTH0(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 27 DUBPTH1 Downstream UTOPIA Backpressure Threshold Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write FFFF H DUBPTH1 32H Written by CPU 13 12 11 10 9 8
DUBPTH1(17:10) Bit 7 6 5 4 3 2 1 0
DUBPTH1(9:2)
DUBPTH1(17:2)
Downstream UTOPIA Backpressure Threshold 1 This bit field determines the backpressure threshold for the Downstream UTOPIA Receive Interface Group 1 (see Chapter 5.2.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: DUBPTH1(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 28 DUBPTH2 Downstream UTOPIA Backpressure Threshold Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write FFFF H DUBPTH2 33H Written by CPU 13 12 11 10 9 8
DUBPTH2(17:10) Bit 7 6 5 4 3 2 1 0
DUBPTH2(9:2)
DUBPTH2(17:2)
Downstream UTOPIA Backpressure Threshold 2 This bit field determines the backpressure threshold for the Downstream UTOPIA Receive Interface Group 2 (see Chapter 5.2.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: DUBPTH2(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description Register 29 DUBPTH3 Downstream UTOPIA Backpressure Threshold Register 3 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write FFFF H DUBPTH3 34H Written by CPU 13 12 11 10 9 8
DUBPTH3(17:10) Bit 7 6 5 4 3 2 1 0
DUBPTH3(9:2)
DUBPTH3(17:2)
Downstream UTOPIA Backpressure Threshold 3 This bit field determines the backpressure threshold for the Downstream UTOPIA Receive Interface Group 3 (see Chapter 5.2.1) with a granularity of 4 cells. The CPU programs the threshold with a granularity of 4 by right shifting the value by 2: DUBPTH3(17:2):= (maximum_cells(17:0) >> 2)
Data Sheet
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Register Description
7.2.8
LCI Table Transfer Registers
Internal Table 1: LCI Table Transfer Registers LCI0, LCI1, LCI2 These registers are used to access the internal Local Connection Identifier (LCI) table containing 16384 entries (one entry serves for upstream and downstream direction). Table 7-4 shows an overview of the registers involved. Table 7-4 47 LCI RAM entry 15 LCI2 15 MASK2 0 15 MASK1 0 15 LCI1 0 15 MASK0 0 15 LCI0 0 15 0 15 MAR=00H LCI select: 0 WAR (0..16383D) Registers for LCI Table Access 0 RAM select: 0
LCI0, LCI1 and LCI2 are the transfer registers for one 48-bit LCI table entry. The LCI value representing the table entry which needs to be read or written must be written to the Word Address Register (WAR). The dedicated LCI table entry is read into the LCI0/ LCI1/LCI2 Registers or modified by the LCI0/LCI1/LCI2 Register values with a write mechanism. The associated Mask Registers MASK0 to MASK2 allow a bit-wise masking for Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated LCI0/LCI1/LCI2 register bit will be overwritten by the respective LCI table entry bit value. In case of Write operation, the dedicated LCI0/LCI1/LCI2 register bit will modify the respective LCI table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the LCI table bit field MAR(4:0) must be set to 0. Bit 5 of the MAR starts the transfer and is automatically cleared after execution. Table 7-5 Bit 15 WAR Register Mapping for LCI Table Access 14 13 12 11 10 9 8
Unused(2:0) Bit 7 6 5 4
LCISel(13:8) 3 2 1 0
LCISel(7:0) LCISel(13:0)
Data Sheet
Selects an LCI entry within the range (0..16383).
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Register Description Register 30 LCI0 LCI Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H LCI0 3BH Written and Read by CPU to maintain the LCI table 14 13 12 11 10 9 8
Unused(13:6) Bit 7 6 5 4 3 2 1 CLPT 0 ABM core
Unused(5:0)
CLPT
CLP Transparent: Specifies whether the CLP bit of cells belonging to this connection is evaluated or not in threshold checks. Valid for both upstream and downstream cores. Does not affect SBOC counters. 0 1 CLP bit is evaluated. CLP bit is not evaluated; all cells are treated as high priority cells assuming CLP=0.
ABMcore
ABM-3G Core Selection: This bit is valid in Uni-directional Mode only and specifies the core responsible for cells of this LCI. 0 1 Scheduler Blocks 0..127 are selected (core 0). Scheduler Blocks 128..255 are selected (core 1).
Data Sheet
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Register Description Register 31 LCI1 LCI Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H LCI1 3CH Written and Read by CPU to maintain the LCI table 14 13 12 11 10 9 8
DnQID(12:5) Bit 7 6 5 DnQID(4:0) DnQID(12:0) 4 3 2 1 Dnflags(2:0) 0
Downstream Queue Identifier. Specifies the queue (0..8191) in which the cells of the connection are stored. Last cell of packet flag for downstream direction; This bit is autonomously used by the EPD function of the ABM-3G. Initialize to 1 at connection setup. Do not Write during normal operation. Discard packet flag in downstream direction; This bit is autonomously used by the EPD function of the ABM-3G. Initialize to 0 at connection setup. Do not Write during normal operation. Discard rest of packet flag in downstream direction; This bit is autonomously used by the EPD function of the ABM-3G. Initialize to 0 at connection setup. Do not Write during normal operation.
Dnflag 2
Dnflag 1
Dnflag 0
Data Sheet
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Register Description Register 32 LCI2 LCI Transfer Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H LCI1 3DH Written and Read by CPU to maintain the LCI table 14 13 12 11 10 9 8
UpQID(12:5) Bit 7 6 5 UpQID(4:0) UpQID(12:0) 4 3 2 1 Upflags(2:0) 0
Upstream Queue Identifier. Specifies the queue (0..8191) in which the cells of the connection are stored. Last cell of packet flag for upstream direction; This bit is autonomously used by the EPD function of the ABM-3G. Initialize to 1 at connection setup. Do not Write during normal operation. Discard packet flag in upstream direction; This bit is autonomously used by the EPD function of the ABM-3G. Initialize to 0 at connection setup. Do not Write during normal operation. Discard rest of packet flag in upstream direction; This bit is autonomously used by the EPD function of the ABM-3G. Initialize to 0 at connection setup. Do not Write during normal operation.
Upflag 2
Upflag 1
Upflag 0
Data Sheet
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Register Description
7.2.9
Traffic Class Table Transfer Registers
Internal Table 2: Traffic Class Table Transfer Registers TCT0, TCT1, TCT2, TCT3 The Traffic Class Table Transfer Registers are used to access the internal Traffic Class Table (TCT) containing 2*16 entries of 4*64 bits each (16 traffic classes per ABM-3G core, 4 words of 64 bits per entry). Table 7-6 shows an overview of the registers involved. Table 7-6 63 TCT RAM entry 15 TCT3 15 MASK3 0 15 MASK2 0 15 TCT2 0 15 MASK1 0 15 TCT1 0 15 MASK0 0 15 TCT0 0 15 WAR (0..127D) 0 15 MAR=01H TCT entry select: 0 Registers for TCT Table Access 0 RAM select: 0
TCT0, TCT1, TCT2 and TCT3 are the transfer registers used to access the 4*64 bit TCT table entries. Core selection, traffic class number, and 64-bit word selection of the table entry which needs to be read or written must be programmed to the Word Address Register (WAR). The dedicated TCT table entry 64-bit word is read into the TCT3/TCT2/TCT1/TCT0 registers or modified by the TCT3/TCT2/TCT1/TCT0 register values with a write mechanism. The associated Mask Registers MASKi (i=3..0) allow a bit-wise masking for Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated TCTi (i=3..0) register bit will be overwritten by the respective TCT table entry bit value. In case of Write operation, the dedicated TCTi (i=3..0) register bit will modify the respective TCT table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the TCT table bit field MAR(4:0) must be set to 1. Bit 5 of MAR starts the transfer and is automatically cleared after execution.
Data Sheet
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Register Description
*
Table 7-7 Bit 15
WAR Register Mapping for TCT Table Access 14 13 12 11 10 9 8
Unused(7:0) Bit 7 6 5 4 3 2 1 0
Unused CoreSel
TCID(3:0)
word64Sel(1:0)
CoreSel
Selects the ABM-3G core for TCT table access: 0 1 Upstream core selected (Core 0) Downstream core selected (Core 1)
TCID(3:0)
Selects The Traffic Class for the TCT table access in the range (0..15). Selects The 64-Bit Word of the 256-bit TCT table entry for access: 00 01 10 11 Bit field (63..0) of traffic class entry is selected. Bit field (127..64) of traffic class entry is selected. Bit field (191..128) of traffic class entry is selected. Bit field (255..192) of traffic class entry is selected.
word64Sel(1:0)
The meaning of registers TCTi (i=3..0) depends on the word selection bit field 'word64Sel(1:0)' in the WAR, because 256-bit TCT entries are mapped to 64 bits of registers TCTi (i=3..0) by this selection:
Data Sheet
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Register Description
*
WAR modulo 4
63
56
55
48
47
40
39
32
3 2 1 TrafClassMax(7:0) 0 DH (2:0)
LostCellsTotal(31:0)1) AcceptedCells/Packets(31:0)1) SBMax(7:0)
unused(3:0)
SBCiCLP1(11:0) unused(15:0)
2 2 2 2 2 2 2 2 2 unused( 876543210 3:0) TCT3(15:0)
TCT2(15:0)
1)
All 5 statistical counters stop at their maximum value. Counters must be set to 0 after read.
WAR modulo 4
31 unused(7:0)
24
23
16
15
8
7
1)
0
3
LostCell LostCell sBuffer sSB(3:0) 1) (3:0)1) QueueMax(7:0) BufCiCLP1(7:0)
LostPackets/CLP1Cells(15:0)
2 1 0
unused(13:0) unused(7:0) unused(7:0)
TrafClassOccNg(17:0)
unused(3:0)
QueueCiCLP1(11:0) BufEPDNg(7:0)
BufMaxNg(7:0)
TCT1(15:0)
1)
TCT0(15:0)
All 5 statistical counters stop at their maximum value. Counters must be set to 0 after read.
Note: - grey fields are 'unused', it is recommended to mask them for write access - green fields must be configured (written) by the CPU - blue fields are statistical counter values optionally read by CPU
Data Sheet
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Register Description Register 33 TCT0 TCT Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H TCT0 3EH Written and Read by CPU to maintain the TCT table; the meaning of register TCT0 depends on the bit field 'Word64Sel' in WAR;
Register WAR.Word64Sel(1:0) ='00': Bit 15 14 13 12 11 10 9 8
BufMaxNg(7:0) Bit 7 6 5 4 3 2 1 0
BufEPDNg(7:0) BufMaxNg(7:0) Maximum Buffer Fill Threshold for a non-real-time traffic class configuration (register TCT1, DwordSel=00). The first cell exceeding this threshold is discarded and if also PPD is enabled for this traffic class (register TCT1, DwordSel=00, PPDen=1) PPD is applied on a per connection (LCI) basis. The threshold is defined with a granularity of 1024 cells: Threshold = BufMaxNg(7:0) * 1024 Cells EPD threshold for a non-real-time traffic class configuration (register TCT1, DwordSel='00'). If the buffer fill exceeds this threshold and EPD is enabled for this traffic class (register TCT1, DwordSel=00, EPDen=1) EPD is applied on a per connection (LCI) basis. The threshold is defined with a granularity of 1024 cells: Threshold = BufEPDNg(7:0) * 1024Cells
BufEPDNg(7:0)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register WAR.Word64Sel(1:0) ='01': Bit 15 14 13 12 11 10 9 8
unused(3:0) Bit 7 6 5 4 3
QueueCiCLP1(11:8) 2 1 0
QueueCiCLP1(7:0) QueueCiCLP1 (11:0) Combined Queue Threshold of this Traffic Class for the following cases: a) if CLPT=0 (CLP transparent bit is not true) and EPDen=0 CLP1 queue threshold for CLP=1 cells (cells with CLP=1 are discarded) b) if CLPT=0 and EPDen=1 EPD GFR queue threshold. If that threshold and additionally BufNrtEPD (of the respective traffic class) is exceeded then EPD is triggered. The threshold is defined with a granularity of 4: Threshold = QueueCiCLP1(7:0) * 4 Cells
*
Register WAR.Word64Sel(1:0) ='10': Bit 15 14 13 12 11 10 9 8
TrafClassOccNg(15:8) Bit 7 6 5 4 3 2 1 0
TrafClassOccNg(7:0) TrafClassOccNg Current Buffer Occupation in number of cells for this traffic class. (15:0) Do not Write in normal operation.
Data Sheet
199
2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Register WAR.Word64Sel(1:0) ='11': Bit 15 14 13 12 11 10 9 8
LostPackets/CLP1Cells(15:8) Bit 7 6 5 4 3 2 1 0
LostPackets/CLP1Cells(7:0) LostPackets/ CLP1Cells (15:0) Count of Lost Packets due to EPD Overflow for this traffic class or count of lost CLP=1 cells due to CLP threshold overflow. Automatically reset after Read access.
Data Sheet
200
2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Register 34 TCT1 TCT Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H TCT1 3FH Written and Read by CPU to maintain the TCT table; the meaning of register TCT1 depends on the bit field 'Word64Sel' in WAR;
Register WAR.Word64Sel(1:0) ='00': Bit 15 14 13 12 11 10 9 8
unused(7:0) Bit 7 6 5 4 3 2 1 0
BufCiCLP1(17:10) BufCiCLP1 (17:10) Buffer EPD CLP1 Threshold This 8-bit value determines a global cell filling level threshold with a granularity of 1024 cells that triggers early packet discard (EPD) for CLP=1 tagged frames used by GFR traffic class service (low watermark). The threshold values are compared with the non guaranteed Buffer Occupancy counters UBufferOccNg, DBufferOccNg respectively. The CPU programs the threshold with a granularity of 1024 cells by right shifting the value by 10: BufCiCLP1(17:10):= (threshold_value(17:0) >> 10) Note: In ABM v1.1 this threshold was determined by registers UEC and DEC.
Data Sheet
201
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ABM-3G PXF 4333 V1.1
Register Description Register WAR.Word64Sel(1:0) ='01': Bit 15 14 13 12 11 10 9 8
unused(7:0) Bit 7 6 5 4 3 2 1 0
QueueMax(7:0) QueueMax (7:0) This 8-bit value determines the maximum queue length with a granularity of 64 cells. The CPU programs the maximum queue length with a granularity of 64 cells by right shifting the value by 6: QueueMax(7:0):= queuelength >> 6 The maximum length of any queue is limited to (255*64) = 16320 cells.
Register WAR.Word64Sel(1:0) ='10': Bit 15 14 13 12 11 10 9 8
unused(7:0) Bit 7 6 5 4 3 2 1 0
unused(5:0)
TrafClassOccNg (17:16)
TrafClassOccNg MSBs of Current Buffer Occupation Counter (17:16) TrafClassOccNg(17:0) counts the number of cells stored for this traffic class. Do not Write in normal operation.
*
Data Sheet
202
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ABM-3G PXF 4333 V1.1
Register Description Register WAR.Word64Sel(1:0) ='11': Bit 15 14 13 12 11 10 9 8
unused(7:0) Bit 7 6 5 4 3 2 1 0
LostCellsBuffer(3:0) LostCellsBuffer (3:0)
LostCellsSB(3:0)
Count of Lost Cells due to Buffer Overflow for this traffic class. Automatically reset after Read access. Count of Lost Cells due to Scheduler Block Overflow for this traffic class. Automatically reset after Read access.
LostCellsSB (3:0)
Data Sheet
203
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ABM-3G PXF 4333 V1.1
Register Description Register 35 TCT2 TCT Transfer Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H TCT2 40H Not used by CPU; the meaning of register TCT2 depends on the bit field 'Word64Sel' in WAR;
Register WAR.Word64Sel(1:0) ='00': Bit 15 14 13 12 11 10 9 8
unused(7:0) Bit 7 6 5 4 3 2 1 0
unused(7:0)
*
Register WAR.Word64Sel(1:0) ='01': Bit 15 14 13 12 11 10 9 8
unused(3:0) Bit 7 6 5 4 3
SBCiCLP1(11:8) 2 1 0
SBCiCLP1(7:0)
Data Sheet
204
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ABM-3G PXF 4333 V1.1
Register Description
SBCiCLP1(11:0)
Scheduler Block Ci/CLP1 Threshold This threshold determines a maximum number of low priority cells allowed to be stored per scheduler block with a granularity of 64 cells. The CPU programs the threshold with a granularity of 64 cells by right shifting the value by 6: SBCiCLP1(11:0):= threshold >> 6
Register WAR.Word64Sel(1:0) ='10': Bit 15 14 13 12 11 10 9 8
AcceptedCells/Packets(15:8) Bit 7 6 5 4 3 2 1 0
AcceptedCells/Packets(7:0) AcceptedCells/ Packets (15:0) Count of Accepted Cells or AAL5 Units within this traffic class, depending on flag SCNT in TCT3. If SCNT = 0: This counter is incremented when a user data cell with AAL_ indication=1 is accepted (Packet end indication in AAL5: PTI= xx1). If SCNT = 1 all accepted cells are counted Do not Write in normal operation. Must be reset after Read access.
*
Data Sheet
205
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ABM-3G PXF 4333 V1.1
Register Description Register WAR.Word64Sel(1:0) ='11': Bit 15 14 13 12 11 10 9 8
LostCellsTotal(15:8) Bit 7 6 5 4 3 2 1 0
LostCellsTotal(7:0) LostCellsTotal (15:0) Count of all lost cells for this traffic class. Do not Write in normal operation. Must be reset after Read access.
Data Sheet
206
2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Register 36 TCT3 TCT Transfer Register 3 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H TCT3 41H Written and Read by CPU to maintain the TCT table; the meaning of register TCT3 depends on the bit field 'Word64Sel' in WAR;
Register WAR.Word64Sel(1:0) ='00': Bit 15 14 DH(2:0) Bit 7 SCNT DH (2:0) 6 0 5 GFRen 13 12 unused 4 0 11 0 3 10 0 2 9 EPDen 1 8 PPDen 0
unused(3:0)
DeltaHysteresis for threshold evaluations with hysteresis applied: This value is per traffic class, but is evaluated individually for each effected threshold TH relative to the threshold size. The hysteresis determines a lower threshold TL with TLi:= THi - Deltai The Deltai value is determined by bit field DH(2:0) and THi with: Deltai:= TH i >> [DH(2:0) +1] The following table shows the operation and resulting TLi values for the example of a threshold programmed to 256 cells: DH(2:0): 0d 1d 2d 3d Deltai:= 0 THi >>2 THi >>3 THi >>4
207
Example: (hysteresis disabled) TLi:= 256 TLi:= 192 TLi:= 224 TLi:= 240
2001-12-17
Data Sheet
ABM-3G PXF 4333 V1.1
Register Description 4d 5d 6d 7d EPDen THi >>5 THi >>6 THi >>7 THi >>8 (hysteresis ineffective) TLi:= 248 TLi:= 252 TLi:= 254 TLi:= 256
EPD for the individual traffic class. EPD is used for every connection (LCI) within that traffic class (see Chapter 3.4.1.6.3): 0 1 EPD is disabled. EPD is enabled.
PPDen
PPD for the individual traffic class. PPD is used for every connection (LCI) within that traffic class (see Chapter 3.4.1.6.3): 0 1 PPD is disabled PPD is enabled
SCNT
Counter Function Select This bit selects the function of counter 'AcceptedCells/ Packets(31:0)': 0 1 Accepted Packets are counted Accepted Cells are counted
GFRen
GFR Enable: This bit enables a modified EPD threshold evaluation for GFR traffic (see Chapter 3.4.1.6.3). 0 1 Modified EPD threshold evaluation for GFR disabled Modified EPD threshold evaluation for GFR enabled
Register WAR.Word64Sel(1:0) ='01': Bit 15 14 13 12 11 10 9 8
TrafClassMax(7:0)
Data Sheet
208
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Register Description
Bit
7
6
5
4
3
2
1
0
SBMax(7:0) TrafClassMax (7:0) Maximum Traffic Class Fill Threshold (determines the maximum number of cells in all queues associated with this traffic class). The threshold is defined with a granularity of 1024: Threshold = TrafClassMax(7:0) * 1024 Cells Combined Threshold of the Maximum Number of Buffered Cells in the Scheduler Block; that is, all cells which are in the traffic classes (= cells in the corresponding queues) of the Scheduler Block for the following cases: a) If EPDen=0 Maximum Scheduler Block fill threshold for CLP='0/1' cells b) If EPDen=1 EPD Scheduler Block threshold The threshold is defined with a granularity of 1024: Threshold = SBMax(7:0) * 1024 Cells
SBMax(7:0)
Register WAR.Word64Sel(1:0) ='10': Bit 15 14 13 12 11 10 9 8
AcceptedCells/Packets(31:24) Bit 7 6 5 4 3 2 1 0
AcceptedCells/Packets(23:16) AcceptedCells/ Packets (31:16) Count of Accepted Cells or AAL5 Units within this traffic class, depending on flag SCNT in TCT3. If SCNT = 0: This counter is incremented when a user data cell with AAL_ indication=1 is accepted (Packet end indication in AAL5: PTI= xx1). If SCNT = 1 all accepted cells are counted Do not Write in normal operation. Must be reset after Read access.
209 2001-12-17
Data Sheet
ABM-3G PXF 4333 V1.1
Register Description
*
Register WAR.Word64Sel(1:0) ='11': Bit 15 14 13 12 11 10 9 8
LostCellsTotal(31:24) Bit 7 6 5 4 3 2 1 0
LostCellsTotal(23:16) LostCellsTotal (31:16) Count of all lost cells for this traffic class. Do not Write in normal operation. Must be reset after Read access.
Data Sheet
210
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ABM-3G PXF 4333 V1.1
Register Description
7.2.10
Queue Configuration Table Transfer Registers
Internal Table 3: Queue Configuration Table Transfer Registers QCT0..6 Queue Configuration Table Transfer Registers are used to access the internal Queue Configuration Table (QCT) containing 2*8192 entries. The lower 8K entries control the upstream core queues and the upper 8K entries control the downstream core queues. Table 7-8 shows an overview of the registers involved. Some fields are not used for entry 0 (common real time bypass) Table 7-8 111 QCT RAM entry 15 0 15 0 15 0 15 0 15 0 15 0 15 0 Registers for Queue Configuration Table Access 0 RAM select: 15 0 QCT1 QCT0 MAR=02 H Queue select: 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 MASK6 =FFFFH MASK5 =FFFFH MASK4 =FFFFH MASK3 =FFFFH MASK2 MASK1 MASK0 =FFFFH WAR (0..16383D)
QCT6
QCT5
QCT4
QCT3
QCT2
QCT0...QCT6 are the transfer registers for one 112 bit QCT table entry. The core selection and queue number representing the table entry which needs to be read or written must be written to the Word Address Register (WAR). The dedicated QCT table entry is read into the QCT0..QCT6 registers or modified by the QCT0..QCT6 register values with a write mechanism. The associated Mask Registers MASK0..MASK6 allow a bit-wise Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated QCT0..QCT6 register bit will be overwritten by the respective QCT table entry bit value. In case of Write operation, the dedicated QCT0..QCT6 register bit will modify the respective QCT table entry bit value. Note: It is recommended not to Write to bit fields (111:64) and (15:0) of the QCT table entries; i.e. registers MASK0, MASK6, MASK5, MASK4 and MASK3 should always be programmed with FFFF H. The 13 LSBs (= Bit 12..0) of the WAR register select the queue-specific entry that will be accessed and bit 'CoreSel' the ABM-3G core. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the QCT table, bit field MAR(4:0) must be set to 2. Bit 5 of MAR starts the transfer and is automatically cleared after execution.
Data Sheet 211 2001-12-17
ABM-3G PXF 4333 V1.1
Register Description Table 7-9 Bit 15 WAR Register Mapping for LCI Table Access 14 13 CoreSel 5 4 3 12 11 10 QSel(12:8) 2 1 0 9 8
unused(1:0) Bit 7 6
QSel(7:0)
CoreSel
Selects an ABM-3G Core: 0 1 Upstream core selected Downstream core selected
QSel(12:0)
Selects a Queue Entry within the range (0..8191).
Data Sheet
212
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ABM-3G PXF 4333 V1.1
Register Description Register 37 QCT0 Queue Configuration Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Unused(1:0) Bit 7 6 5 4 Read/Write 0000 H QCT0 Read by CPU 14 13 12 11 10 9 8 42H
QueueLength(13:8) 3 2 1 0
QueueLength(7:0) QueueLength (13:0) Represents the Current Number of Cells Stored in this Queue. Do not Write in normal operation.
Data Sheet
213
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ABM-3G PXF 4333 V1.1
Register Description Register 38 QCT1 Queue Configuration Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 DQac Bit 7 QIDvalid DQac Dummy Queue Action This bit is a command bit that must always be set when a dummy queue is activated or deactivated. Note: Read access to this command bit will always return '0'. RSall ReSchedule Always This bit determines the queue scheduling process: '0' The queue is only scheduled/re-scheduled with its specific rate while the queue is not empty (normal operation). Read/Write 0000 H QCT1 43H Written and Read by CPU to maintain the LCI table 14 RSall 6 13 0 5 12 0 4 3 SBID(6:0) 11 10 9 8
TCID(3:0) 2 1 0
Data Sheet
214
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ABM-3G PXF 4333 V1.1
Register Description '1' The queue is always scheduled/re-scheduled with its specific rate independent of the queue filling level. Scheduling an empty queue results in an 'empty cell cycle' (no cell is emitted during this cycle). A so called 'dummy queue' is used for generating empty cell cycles. Note: 'RSall' can be set with connection setup (together with QIDvalid='1') or anytime while the queue is enabled. After setting bit 'RSall', the ABM-3G will automatically set bit 'MGconf/DQsch' to acknowledge the first dummy schedule event. The 'RSall' information is internally conveyed to the scheduler. This process is acknowledged by an interrupt (Bit 'UDQRD/DDQRD' in Register 103: ISRC). It is recommended not to select any other table or table entry while waiting for this acknowledge. Note: 'RSall' can be reset anytime while the queue is enabled. In response to resetting 'RSall' the ABM-3G will generate an interrupt (Bit 'UDQRD/ DDQRD' in Register 103: ISRC) and reset bit 'MGconf/DQsch' in this table. Note: To activate or deactivate a dummy queue, command bit 'DQac' must be set in conjunction with setting or resetting bit 'RSall'.
QIDvalid
Queue Enable:
Data Sheet
215
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ABM-3G PXF 4333 V1.1
Register Description 0 Queue disabled. An attempt to store a cell to a disabled queue leads to discard of the cell and a QIDINV interrupt is generated. If a filled queue gets disabled, cells may still be in the queue. In this case the disabled queue is still scheduled, and cells are logically emitted from the queue but will not be transmitted. Actual filling of the queue can be obtained via QueueLength(13:0) parameter in the QCT entry. Note: To disable an active VC-merge group, bit 'QIDvalid must be reset. Deactivating the queue by setting QIDvalid='0' automatically starts an internal process to delete the queue from the VCmerge group. In response to resetting 'QIDvalid' the ABM-3G will generate an interrupt (Bit 'UQVCMGD/DQVCMGD' in Register 103: ISRC) and reset bit 'MGconf/DQsch' in this table. 1 Queue enabled. Cells are allowed to enter the queue.
TCID(3:0)
Traffic Class Number (0..15) Assigns the queue to one of the 16 traffic classes defined in the traffic class table TCT for this core. Scheduler Block Number (0..127) Assigns the queue to one of the 128 schedulers of this core.
SBID(6:0)
*
Data Sheet
216
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Register Description Register 39 QCT2 Queue Configuration Transfer Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 MGconf/ DQsch Bit 7 6 5 4 Read/Write 0000 H QCT2 44H Written by CPU to configure VC-Merge operation 14 13 12 11 MGID(6:0) 10 9 8
3
2
1
0
MinBG(7:0) MGconf/DQsch Merge Group Configured/ Dummy Queue Scheduled The meaning of this flag depends on bit 'RSall': RSall='0' The queue is not configured as a 'dummy queue' and may be configured as a VC-merge group member: MGconf 0 1 The queue is neither a dummy queue, nor member of a VC-merge group. The queue is member of a VC-merge group. The VCmerge group is determined by bit field 'MGID(6:0). Note: To disable an active VC-merge group, bit 'QIDvalid' must be reset. Deactivating the queue by setting QIDvalid='0' automatically starts an internal process to delete the queue from the VCmerge group. In response to resetting 'QIDvalid' the ABM-3G will generate an interrupt (Bit 'UQVCMGD/DQVCMGD' in Register 103: ISRC) and reset bit 'MGconf/DQsch' in this table. RSall='1' The queue is configured as a 'dummy queue': DQsch
Data Sheet 217 2001-12-17
ABM-3G PXF 4333 V1.1
Register Description 0 1 The queue is activated as a 'dummy queue', but no first dummy schedule event has occurred. The queue is activated as a 'dummy queue' and at least one first dummy schedule event has occurred. Note: 'RSall' can be reset anytime while the queue is enabled. In response to resetting 'RSall' the ABM-3G will generate an interrupt (Bit 'UDQRD/ DDQRD' in Register 103: ISRC) and reset bit 'MGconf/DQsch' in this table. MGID(6:0) Merge Group Number (0..127) Assigns the queue to one of 128 merge groups of this core. Minimum Buffer Guarantee This bit field determines a minimum buffer reservation for this particular queue. The sum of all minimum buffer reservations virtually divides the total buffer into a 'Guaranteed' part and a shared 'Non-Guaranteed' part. The minimum buffer reservation offers to granularities depending on MSB of MinBG(7): MinBG(7) Granularity of 1 cell for short queues (e.g. real-time := 0 queues): The minimum reserved buffer in number of cells is reserved_buffer = MinBG(6:0) = {0,1,2,..127} MinBG(7) Granularity of 8 cells for long queues (e.g. non-real-time := 1 queues): The minimum reserved buffer in number of cells is reserved_buffer = MinBG(6:0) << 3 = {0,8,16,..1016}
MinBG(7:0)
Data Sheet
218
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ABM-3G PXF 4333 V1.1
Register Description Register 40 QCT3 Queue Configuration Transfer Register 3
*
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15
Read/Write 0000 H QCT3 45H Not used by CPU 14 13 12 11 10 9 8
unused(11:4) Bit 7 6 5 4 3 EOP 2 reserve d 1 reserve d 0 reserve d
unused(3:0)
EOP
EOP-Flag: Do not Write during normal operation.
Data Sheet
219
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ABM-3G PXF 4333 V1.1
Register Description Register 41 QCT4 Queue Configuration Transfer Register 4 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H QCT4 46H Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0) Reserved(15:0) Do not Write in normal operation.
Data Sheet
220
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ABM-3G PXF 4333 V1.1
Register Description Register 42 QCT5 Queue Configuration Transfer Register 5 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H QCT5 47H Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0) reserved(15:0) Do not Write in normal operation.
Data Sheet
221
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Register Description Register 43 QCT6 Queue Configuration Transfer Register 6 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H QCT6 48H Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0) reserved(15:0) Do not Write in normal operation.
Data Sheet
222
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Register Description
7.2.11
Scheduler Block Occupancy Table Transfer Registers
Internal Table 4: Scheduler Block Occupancy Table Transfer Registers SBOC0..SBOC4 The Scheduler Block Occupancy Table Transfer Registers are used to access the internal Scheduler Block Occupancy Table (SBOC) containing 2*128 entries of 80 bit each. Table 7-10 shows an overview of the registers involved. Note: The SBOC table information is typically not required by the CPU. The SBOC maintains global counters that are internally used for threshold evaluation. For statistical purposes, reading the SBOC entries provides a snap shot of the respective scheduler occupation situation distinguished by priorities and also the current number of discarded low priority cells. Table 7-10 79 SBOC RAM entry 15 SBOC4 15 MASK4 0 15 SBOC3 0 15 MASK3 0 15 SBOC2 0 15 MASK2 0 15 SBOC1 0 15 MASK1 0 15 SBOC0 0 15 MASK0 0 15 0 Registers for SBOC Table Access 0 RAM Select: 15 MAR=03H Entry select: 0 WAR (0..255D) 0
SBOC0..SBOC4 are the transfer registers for one 80-bit SBOC table entry. The Scheduler Block number representing the table entry which needs to be read or written must be written to the Word Address Register (WAR). The dedicated SBOC table entry is read into the SBOC0..SBOC4 Registers or modified by the SBOC0..SBOC4 register values with a write mechanism. The associated Mask Registers MASK0..MASK4 allow a bit-wise Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated SBOC0..SBOC4 register bit will be overwritten by the respective SBOC table entry bit value. In case of Write operation, the dedicated SBOC0..SBOC4 register bit will modify the respective SBOC table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to select the SBOC table, bit field MAR(4:0) must be set to 3. Bit 5 of MAR starts the transfer and is automatically cleared after execution.
Data Sheet
223
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ABM-3G PXF 4333 V1.1
Register Description Table 7-11 Bit 15 WAR Register Mapping for SBOC Table Access 14 13 12 11 10 9 8
Unused(7:0) Bit 7 CoreSel 6 5 4 3 SchedSel(6:0) 2 1 0
CoreSel
Selects an ABM-3G core: 0 1 Upstream core selected Downstream core selected
SchedSel(6:0)
Selects one of the 128 core-specific Scheduler Blocks.
Data Sheet
224
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ABM-3G PXF 4333 V1.1
Register Description Register 44 SBOC0 SBOC Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read only 0000 H SBOC0 Read by CPU 14 13 12 11 10 9 8 49H
SBOccNg(1:0) Bit 7 6
SBOccHP(1:0) 5 4
SBOccLP(1:0) 3 2
SBOccLPd(1:0) 1 0
Reserved(7:0)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 45 SBOC1 SBOC Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H SBOC1 4AH Read by CPU (for debug purposes or statistics) 14 13 12 11 10 9 8
SBOccLPd(17:10) Bit 7 6 5 4 3 2 1 0
SBOccLPd(9:2) SBOccLPd (17:2) Scheduler Block Occupancy Counter Low Priority Discarded Cells The Counter is reset if both SBOccLP and SBOccHP are equal 0. Note: The LSBs SBOccLPd(1:0) are mapped to transfer register SBOC0.
Data Sheet
226
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ABM-3G PXF 4333 V1.1
Register Description Register 46 SBOC2 SBOC Transfer Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H SBOC1 4BH Read by CPU (for debug purposes or statistics) 14 13 12 11 10 9 8
SBOccLP(17:10) Bit 7 6 5 4 3 2 1 0
SBOccLP(9:2) SBOccLP(17:2) Scheduler Block Occupancy Counter Low Priority Note: The LSBs SBOccLP(1:0) are mapped to transfer register SBOC0.
Data Sheet
227
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ABM-3G PXF 4333 V1.1
Register Description Register 47 SBOC3 SBOC Transfer Register 3
*
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15
Read/Write 0000 H SBOC3 4CH Read by CPU (for debug purposes or statistics) 14 13 12 11 10 9 8
SBOccHP(17:10) Bit 7 6 5 4 3 2 1 0
SBOccHP(9:2) SBOccHP(17:2) Scheduler Block Occupancy Counter High Priority Note: The LSBs SBOccHP(1:0) are mapped to transfer register SBOC0.
Data Sheet
228
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Register Description Register 48 SBOC4 SBOC Transfer Register 4
*
CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15
Read/Write 0000 H SBOC4 4DH Read by CPU (for debug purposes or statistics) 14 13 12 11 10 9 8
SBOccNg(17:10) Bit 7 6 5 4 3 2 1 0
SBOccNg(9:2) SBOccNg(17:2) Scheduler Block Occupancy Counter Non Guaranteed Note: The LSBs SBOccNg(1:0) are mapped to transfer register SBOC0.
Data Sheet
229
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Register Description
7.2.12
Merge Group Table Transfer Registers
Internal Table 5: Merge Group Table Transfer Registers MGT0..MGT2 The Merge Group Table Transfer Registers are used to access the internal Merge Group Table (MGT) containing 2*128 entries of 48 bit each. Table 7-10 shows an overview of the registers involved. Table 7-12 47 MGT RAM entry 15 MGT2 15 MASK2 0 15 MASK1 0 15 MGT1 0 15 MASK0 0 15 MGT0 0 15 0 15 MAR=07H Entry select: 0 WAR (0..255D) Registers for MGT Table Access 0 RAM Select: 0
MGT0..MGT2 are the transfer registers for one 48-bit MGT table entry. The Scheduler Block number representing the table entry which needs to be read or written must be written to the Word Address Register (WAR). The dedicated MGT table entry is read into the MGT0..MGT2 Registers or modified by the MGT0..MGT2 register values with a write mechanism. The associated Mask Registers MASK0..MASK2 allow a bit-wise Write operation (0 - unmasked, 1 - masked). In case of read operation, the dedicated MGT0..MGT2 register bit will be overwritten by the respective MGT table entry bit value. In case of Write operation, the dedicated MGT0..MGT2 register bit will modify the respective MGT table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to select the MGT table, bit field MAR(4:0) must be set to 6. Bit 5 of MAR starts the transfer and is automatically cleared after execution.
Data Sheet
230
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ABM-3G PXF 4333 V1.1
Register Description Table 7-13 Bit 15 WAR Register Mapping for MGT Table Access 14 13 12 11 10 9 8
Unused(7:0) Bit 7 CoreSel 6 5 4 3 GroupSel(6:0) 2 1 0
CoreSel
Selects an ABM-3G core: 0 1 Upstream core selected Downstream core selected
GroupSel(6:0)
Selects one of the 128 Merge Groups.
Data Sheet
231
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ABM-3G PXF 4333 V1.1
Register Description Register 49 MGT0 MGT Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H MGT0 4EH Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0) Reserved(15:0)
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Register Description Register 50 MGT1 MGT Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H MGT1 4FH Not used by CPU 14 Reserved(15:13) Bit 7 6 5 4 13 12 11 10 9 8
Head_Pointer(12:8) 3 2 1 0
Head_Pointer(7:0) Reserved(15:13) Head_Pointer(12:0) When setting up a merge group, this pointer must be set to point to any of the queues contained in the merge group.
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Register Description Register 51 MGT2 MGT Transfer Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 unused Bit 7 Read/Write 0000 H MGT2 50H Written by CPU to maintain the MGT table 14 LCIOen 6 5 4 LCI(7:0) LCIOen LCI Overwrite Enable: This bit enables the LCI overwrite function for cells/packets emitted by the VC-Merge Group. 0 1 LCI(13:0) Disable LCI overwrite Enable LCI overwrite 13 12 11 10 9 8
LCI(13:8) 3 2 1 0
LCI In case LCI overwrite function is enabled, this value overwrites the original LCI of any cell emitted by this VC-Merge Group. The cell field that is overwritten depends on the selected LCI mapping mode.
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Register Description
7.2.13
Mask Registers
Register 52 MASK0/MASK1 Table Access Mask Registers 0/1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H MASK0 55H MASK1 56H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
MASK(15:8) Bit 7 6 5 4 3 2 1 0
MASK(7:0)
MASK0(15:0) MASK1(15:0)
Mask Register 0 Mask Register 1 Mask Registers 0..6 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6, SBOC0..SBOC4, MGT0..MGT2): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 53 MASK2/MASK3 Table Access Mask Registers 2/3 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H MASK2 57H MASK3 58H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
MASK(15:8) Bit 7 6 5 4 3 2 1 0
MASK(7:0) MASK2(15:0) MASK3(15:0) Mask Register 2 Mask Register 3 Mask Registers 0..6 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6, SBOC0..SBOC4, MGT0..MGT2): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 54 MASK4/MASK5 Table Access Mask Registers 4/5 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H MASK4 59H MASK5 5AH Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
MASK(15:8) Bit 7 6 5 4 3 2 1 0
MASK(7:0)
MASK4(15:0) MASK5(15:0)
Mask Register 4 Mask Register 5 Mask Registers 0..6 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6, SBOC0..SBOC4, MGT0..MGT2): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 55 MASK6 Table Access Mask Registers 6 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H MASK6 5BH Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
MASK(15:8) Bit 7 6 5 4 3 2 1 0
MASK(7:0)
MASK6(15:0)
Mask Register 6 Mask Registers 0..6 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6, SBOC0..SBOC4, MGT0..MGT2): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description
7.2.14
Rate Shaper CDV Registers
Register 56 UCDV/DCDV Upstream/Downstream Rate Shaper CDV Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UCDV 62H DCDV 82H Written by CPU 14 13 12 Unused(6:0) 11 10 9 8 CDV Max(8) 3 2 1 0
Bit
7
6
5
4
CDVMax(7:0) CDVMax(8:0) Maximal Cell Delay Variation (without notice) This bit field determines a maximum CDV value for peak rate limited queues that can be introduced without notice. The CDVMax is measured in multiples of 16-cell cycles. If this maximum CDV is exceeded, a CDVOV (see registers ISRU/ ISRD) interrupt is generated to indicate an unexpected CDV value. This can occur if multiple peak rate limited queues are scheduled to emit a cell in the same Scheduler time slot. No cells are discarded due to this event.
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Register Description
7.2.15
Queue Parameter Table Mask Registers
Register 57 UQPTM0/DQPTM0 Upstream/Downstream Queue Parameter Table Mask Registers 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H UQPTM0 65H DQPTM0 85H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
xQPTM0(15:8) Bit 7 6 5 4 3 2 1 0
xQPTM0(7:0) UQPTM0(15:0) DQPTM0(15:0) Upstream QPT Mask Register 0 Downstream QPT Mask Register 0 UQPTM0/DQPTM0 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (UQPT1T0/UQPT2T0, DQPT1T0/DQPT2T0): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 58 UQPTM1/DQPTM1 Upstream/Downstream Queue Parameter Table Mask Registers 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPTM1 66H DQPTM1 86H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
xQPTM1(15:8) Bit 7 6 5 4 3 2 1 0
xQPTM1(7:0) UQPTM1(15:0) DQPTM1(15:0) Upstream QPT Mask Register 1 Downstream QPT Mask Register 1 UQPTM1/DQPTM1 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (UQPT1T1/UQPT2T1, DQPT1T1/DQPT2T1): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 59 UQPTM2/DQPTM2 Upstream/Downstream Queue Parameter Table Mask Registers 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPTM2 67H DQPTM2 87H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
xQPTM2(15:8) Bit 7 6 5 4 3 2 1 0
xQPTM2(7:0) UQPTM2(15:0) DQPTM2(15:0) Upstream QPT Mask Register 2 Downstream QPT Mask Register 2 UQPTM2/DQPTM2 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (UQPT2T2, DQPT2T2): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 60 UQPTM3/DQPTM3 Upstream/Downstream Queue Parameter Table Mask Registers 3 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H UQPTM3 68H DQPTM3 88H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
xQPTM3(15:8) Bit 7 6 5 4 3 2 1 0
xQPTM3(7:0) UQPTM3(15:0) DQPTM3(15:0) Upstream QPT Mask Register 3 Downstream QPT Mask Register 3 UQPTM3/DQPTM3 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (UQPT2T3, DQPT2T3): 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 61 UQPTM4/DQPTM4 Upstream/Downstream Queue Parameter Table Mask Registers 4 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPTM4 69H DQPTM4 89H Not used for user-accessible tables. 14 13 12 11 10 9 8
xQPTM4(15:8) Bit 7 6 5 4 3 2 1 0
xQPTM4(7:0) UQPTM4(15:0) DQPTM4(15:0) Upstream QPT Mask Register 4 Downstream QPT Mask Register 4 UQPTM4/DQPTM4 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers: 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description Register 62 UQPTM5/DQPTM5 Upstream/Downstream Queue Parameter Table Mask Registers 5 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPTM5 6AH DQPTM5 8AH Not used for user-accessible tables. 14 13 12 11 10 9 8
xQPTM5(15:8) Bit 7 6 5 4 3 2 1 0
xQPTM5(7:0) UQPTM5(15:0) DQPTM5(15:0) Upstream QPT Mask Register 5 Downstream QPT Mask Register 5 UQPTM5/DQPTM5 control the Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers: 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
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Register Description
7.2.16
Scheduler Configuration Register
Register 63 USCONF/DSCONF Upstream/Downstream Scheduler Configuration Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0004 H USCONF 6BH DSCONF 8BH Written by CPU during global initialization 14 13 12 11 10 9 8
unused(12:5) Bit 7 6 5 unused(4:0) TstepC(2:0) 4 3 2 1 TstepC(2:0) 0
Time Base for the Rate Shaper Refer to Section 4.2.2.5 "Programming the PCR Limiter" on Page 109
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Register Description
7.2.17
Queue Parameter Table Transfer Registers
Internal Table 6: Queue Parameter Table 1 Transfer Registers Queue Parameter Table Transfer Registers are used to access the internal Upstream and Downstream Queue Parameter Table 1 (QPT1) containing 8192 entries each. In both Table 7-14 and Table 7-15 provide an overview of the registers involved. Each QPT1 entry consists of 32 bits. Note: The QPT1 table information is not used by the CPU beside during queue initialization. Table 7-14 31 QPT1 RAM entry (Upstream) 15 UQPT1T1 15 UQPTM1 0 15 UQPTM0 0 15 UQPT1T0 0 15 0 15 MAR=10H Entry Select: 0 WAR (0..8191D) Registers for QPT1 Upstream Table Access 0 RAM Select: 0
*
Table 7-15 31
Registers for QPT1 Downstream Table Access 0 RAM Select: 0 DQPT1T0 0 15 0 DQPTM0 15 15 MAR=18H Entry Select: 0 0
QPT1 RAM entry (Downstream) 15 DQPT1T1 15 DQPTM1 0 15
WAR (0..8191D)
UQPT1T0 and UQPT1T1 are the transfer registers for the 32-bit entry of the upstream QPT1 table. DQPT1T0 and DQPT1T1 are the transfer registers for the 32-bit entry of the downstream QPT1 table. Access to high and low word are both controlled by mask registers UQPTM0/UQPTM1 and DQPTM0/DQPTM1 respectively. The Mask registers are shared for access to both tables QPT1 and QPT2, whereas, the transfer registers are unique for each table.
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Register Description The queue number representing the table entry which needs to be read or written must be written to the Word Address Register (WAR). The dedicated QPT1 table entry is read into the xQPT1T0/xQPT1T1 transfer registers (x=U,D) or modified by the xQPT1T0/ xQPT1T1 transfer register values with a write mechanism. The associated mask registers xQPTM0 and xQPTM1 allow a bit-wise Write operation (0 - unmasked, 1 masked). In case of Read operation, the dedicated xQPT1T0/xQPT1T1 register bit will be overwritten by the respective QPT1 table entry bit value. In case of Write operation, the dedicated xQPT1T0/xQPT1T1 register bit will modify the respective QPT1 table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to select the QPT table bit field MAR(4:0) must be set to: 10H for QPT1 upstream table, 18H for QPT1 downstream table. Bit 5 of MAR starts the transfer and is cleared automatically after execution. Table 7-16 Bit 15 WAR Register Mapping for QPT Table Access 14 Unused(2:0) Bit 7 6 5 4 3 13 12 11 10 QueueSel(12:8) 2 1 0 9 8
QueueSel(7:0)
QueueSel(12:0)
Selects one of the 8192 queue parameter table entries.
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Register Description Register 64 UQPT1T0/DQPT1T0 Upstream/Downstream QPT1 Table Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPT1T0 70H DQPT1T0 90H Written by CPU during queue initialization 14 13 12 11 10 9 8
Reserved(13:6) Bit 7 6 5 4 3 2 1 0
Reserved(5:0)
flags(1:0)
Reserved(13:0)
These bits are used by the device logic. Do not Write to this field as that could lead to complete malfunctioning of the ABM-3G which can be corrected by chip reset only. These bits must be written to 0 when initializing the queue. Do not Write during normal operation.
flags(1:0)
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Register Description Register 65 UQPT1T1/DQPT1T1 Upstream/Downstream QPT1 Table Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPT1T1 71H DQPT1T0 91H Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0)
Reserved(15:0)
These bits are used by the device logic. Do not Write to this field as that could lead to complete malfunctioning of the ABM-3G which can be corrected by chip reset only.
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Register Description Internal Table 7: Queue Parameter Table 2 Transfer Registers Queue Parameter Table Transfer Registers are used to access the internal Upstream and Downstream Queue Parameter Table 2 (QPT2) containing 8192 entries each. In both Table 7-17 and Table 7-18 provide an overview of the registers involved. Each QPT2 entry consists of 64 bits. Table 7-17 63 QPT2 RAM entry (Upstream) 15 UQPT2T3 15 UQPTM3 0 15 UQPT2T2 0 15 UQPTM2 0 15 UQPT2T1 0 15 UQPTM1 0 15 UQPT2T0 0 15 UQPTM0 0 15 WAR (0..8191D) 0 15 MAR=11 H Entry Select: 0 Registers for QPT2 Upstream Table Access 0 RAM Select: 0
*
Table 7-18 63
Registers for QPT2 Downstream Table Access 0 QPT2 RAM entry (Downstream) RAM Select: 0 15 MAR=19 H Entry Select: 0 15 WAR (0..8191D) 0 0 DQPT2T0 0 15 DQPTM1 DQPTM0 0 15 DQPT2T2 0 15 DQPTM2 0 15 DQPT2T1 0 15 0 15
15 DQPT2T3 15 DQPTM3
UQPT2T0..UQPT2T3 are the transfer registers for the 64-bit entry of the upstream QPT2 table. DQPT2T0..DQPT2T3 are the transfer registers for the 64-bit entry of the downstream QPT2 table. Access to the RAM entry is controlled by mask registers UQPTM0..UQPTM3 and DQPTM0..DQPTM3, respectively. The Mask registers are shared for access to both tables QPT1 and QPT2 whereas the transfer registers are unique for each table. The queue number representing the table entry which needs to be read or written must be written to the Word Address Register (WAR). The dedicated QPT2 table entry is read into the xQPT2T0..xQPT2T3 transfer registers (x=U,D) or modified by the xQPT2T0..xQPT2T3 transfer register values with a write mechanism. The associated mask registers xQPTM0..xQPTM3 allow a bit-wise Write operation (0 - unmasked, 1 Data Sheet 251 2001-12-17
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Register Description masked). In case of Read operation, the dedicated xQPT2T0..xQPT2T3 register bit will be overwritten by the respective QPT1 table entry bit value. In case of Write operation, the dedicated xQPT2T0..xQPT2T3 register bit will modify the respective QPT1 table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to select the QPT table bit field MAR(4:0) must be set to: 11H for QPT2 upstream table, 19H for QPT2 downstream table. Bit 5 of MAR starts the transfer and is cleared automatically after execution. Table 7-19 Bit 15 WAR Register Mapping for QPT Table Access 14 Unused(2:0) Bit 7 6 5 4 3 13 12 11 10 QueueSel(12:8) 2 1 0 9 8
QueueSel(7:0)
QueueSel(12:0)
Selects one of the 8192 queue parameter table entries.
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Register Description Register 66 UQPT2T0/DQPT2T0 Upstream/Downstream QPT2 Table Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPT2T0 72H DQPT2T0 92H Written by CPU during queue initialization 14 13 12 11 10 9 8
RateFactor(15:8) Bit 7 6 5 4 3 2 1 0
RateFactor(7:0) RateFactor(15:0) Controls the Peak Cell Rate of the queue. It is identical to the Rate factor TP described in Section 4.2.2.5 "Programming the PCR Limiter" on Page 109. The value 0 disables the PCR limiter, that is, the cells from this queue bypass the shaper circuit. For VBR shaping, this parameter is not used (overridden by the parameter TP of the AVT table). However, it must be set unequal to 0 to enable VBR shaping.
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Register Description Register 67 UQPT2T1/DQPT2T1 Upstream/Downstream QPT2 Table Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPT2T1 73H DQPT2T1 93H Written by CPU during queue initialization 14 13 12 11 10 9 8
Unused(1:0) Bit 7 6 5 4
WFQFactor(13:8) 3 2 1 0
WFQFactor(7:0)
WFQFactor (13:0)
Determines the weight factor TWFQ of the queue at the WFQ scheduler input to which it is connected. Refer to Section 4.2.2.7 "Guaranteed Cell Rates and WFQ Weight Factors" on Page 114. The value WFQ Factor = 0 connects the queue to the high priority Round Robin Scheduler. The value WFQFactor = 16383 (all ones) connects the queue to the low priority Round Robin Scheduler. Modifying the WFQFactor during operation: * If one of the Round Robin Schedulers (WFQFactor=0 or WFQFactor=16383) is used the WFQFactor must not be changed * If the WFQ Scheduler (WFQFactor=1..16320) is used the WFQFactor may be varied in a range 1 to 16320.
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Register Description Register 68 UQPT2T2/DQPT2T2 Upstream/Downstream QPT2 Table Transfer Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPT2T2 74H DQPT2T2 94H Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0)
Reserved(15:0)
These bits are used by the device logic. Do not Write to this field as that could lead to complete malfunctioning of the ABM-3G, which can be corrected by chip reset only.
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Register Description Register 69 UQPT2T3/DQPT2T3 Upstream/Downstream QPT2 Table Transfer Register 3 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UQPT2T3 75H DQPT2T3 95H Not used by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0)
Reserved(15:0)
These bits are used by the device logic. Do not Write to this field as that could lead to complete malfunctioning of the ABM-3G, which can be corrected by chip reset only.
Data Sheet
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Register Description
7.2.18
Scheduler Block Configuration Table Transfer/Mask Registers SDRAM Refresh Registers UTOPIA Port Select of Common Real Time Queue Registers
Internal Table 8: Scheduler Configuration Table Integer Transfer Registers The Scheduler Configuration Table Integer Transfer Registers are used to access the internal Upstream/Downstream Scheduler Configuration Tables Integer Part (SCTI) containing 128 entries each. These tables are not addressed by the MAR and WAR registers, but are addressed via dedicated address registers (USADR/DSADR) and data registers (USCTI/DSCTI). Table 7-20 and Table 7-21 show an overview of the registers involved. Table 7-20 31 SCTI RAM entry (Upstream) 15 USCTI 0 Registers SCTI Upstream Table Access 0 RAM/Entry/Word select: 15 USADR (WSEL=1) 15 USCTI 0 15 USADR (WSEL=0) 0 0
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Register Description Table 7-21 31 SCTI RAM Entry (Downstream) 15 DSCTI 0 Registers SCTI Downstream Table Access 0 RAM/Entry/Word select: 15 DSADR (WSEL=1) 15 DSCTI 0 15 DSADR (WSEL=0) 0 0
USCTI and DSCTI are the transfer registers for the 32-bit SCTI upstream/downstream table entries. The upstream and downstream Schedulers use different tables (internal RAM) addressed via dedicated registers, USADR/DSADR. The address registers select the scheduler-specific entry as well as the high or low word of a 32-bit entry to be accessed. Further, there is no command bit, but transfers are triggered via Write access of the address registers and the data registers: * To initiate a Read access, the Scheduler Block number must be written to the address register USADR (upstream) or to the address register DSADR (downstream). One system clock cycle later, the data can be Read from the respective transfer register USCTI or DSCTI. * To initiate a Write access, it is sufficient to Write the desired Scheduler Block number to the address registers, USADR and DSADR, and then Write the desired data to the respective transfer register, USCTI or DSCTI, respectively. The transfer to the integer table is executed one system clock cycle after the Write access to USCTI or DSCTI. Thus, consecutive Write cycles may be executed by the microprocessor. The SCTI table entries are either read or written. Thus, no additional mask registers are provided for bit-wise control of table entry accesses.
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Register Description Register 70 USADR/DSADR Upstream/Downstream SCTI Address Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USADR A0H DSADR B8H Written and Read by CPU to maintain the SCTI tables 14 13 12 11 10 9 8
unused(7:0) Bit 7 WSel WSel 6 5 4 3 SchedNo(6:0) SCTI table entry Word Select 1 0 Selects the high word (bit 31..16) for next access via register SCTIU/SCTID Selects the low word (bit 15..0) for next access via register SCTIU/SCTID 2 1 0
SchedNo(6:0)
Scheduler Block Number Selects one of the 128 core-specific Scheduler Blocks for next access via register USCTI/DSCTI.
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Register Description Register 71 USCTI/DSCTI Upstream/Downstream SCTI Transfer Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H USCTI A1H DSCTI B9H Written by CPU to maintain the SCTI tables
Register SADRx.WSel = 0: Bit 15 14 13 12 11 10 9 8
unused(1:0) Bit 7 6 5 4
IntRate(13:8) 3 2 1 0
IntRate(7:0) IntRate(13:0) Integer Rate This value determines the integer part of the Scheduler Block output rate.
Note: Recommendation for changing the UTOPIA port number or scheduler rate during operation: Disable specific scheduler by read-modify-write operation to corresponding bit in registers USCEN0/DSCEN0... USCEN7/DSCEN7. Modify scheduler specific UTOPIA port number and rates via Table 8 "Scheduler Configuration Table Integer Transfer Registers" on Page 257, registers USCTI/DSCTI and Table 9 "Scheduler Configuration Table Fractional Transfer Registers" on Page 267, registers USCTFT/DSCTFT. Enable specific scheduler by read-modify-write operation to corresponding bit in registers USCEN0/DSCEN0... USCEN7/DSCEN7. Note: Read access to bit field IntRate(13:0) is not supported and will return undefined values. Refer to Section 4.2.2.2 "Programming the Scheduler Block Rates" on Page 106 for the calculation of IntRate and FracRate
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Register Description Register SADRx.WSel = 1: Bit 15 14 13 12 Init(9:2) Bit 7 Init(1:0) Init(9:0) 6 5 4 3 2 1 0 11 10 9 8
UTOPIAPort(5:0) Initialization Value It is recommended to Write this bit field to all 0s during Scheduler Block configuration/initialization (the note below provides the details).
UTOPIAPort(5:0) UTOPIA Port Number Specifies one of the 48 UTOPIA ports to which the Scheduler Block is assigned to. Only values in the range 0..47D are valid (0..3 for UTOPIA level 1). The UTOPIA port number value can be changed during operation (see note below). UTOPIA Port 48D is used to select the AAL5 reassembly unit.
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Register Description The UTOPIA port number can be modified during operation; (port) switch-over is e.g. used for ATM protection switching. The following Notes explain switch-over and rate adaptation during operation: Note: This SCTI table entry should be programmed during Scheduler Block configuration/initialization. However the UTOPIA port number value can be modified during operation (e.g. for port switching). In this case the Init(9:0) value can be reset to 0. This bit field contains a 4-bit counter incrementing the number of unused scheduler cell cycles. Unused cell cycles occur whenever a scheduled event cannot be served, because a previously generated event is still in service (active cell transfer at UTOPIA Interface). This counter value is used (and decremented accordingly) to determine the allowed cell burst size for following scheduler events. Such bursts are treated as 'one event' to allow a near 100% scheduler rate utilization. The maximum burst size is programmed in registers UECRI/DECRI on page 7-263. Thus, overwriting bit field Init(9:0) with 0 during operation may invalidate some stored cell cycles, only if maximum burst size is programmed >1 for this port. Only saved scheduler cell cycles can get lost; in no way can stored cells be lost or discarded by these operations. To minimize even this small impact, value Init(9:0) can be read and written back with the new UTOPIA port number. Note: Recommendation for changing the UTOPIA port number or scheduler rate during operation: Disable specific scheduler by read-modify-write operation to corresponding bit in registers USCEN0/DSCEN0... USCEN7/DSCEN7. Modify scheduler specific UTOPIA port number and rates via Table 8 "Scheduler Configuration Table Integer Transfer Registers" on Page 257, registers USCTI/DSCTI and Table 9 "Scheduler Configuration Table Fractional Transfer Registers" on Page 267, registers USCTFT/DSCTFT. Enable specific scheduler by read-modify-write operation to corresponding bit in registers USCEN0/DSCEN0... USCEN7/DSCEN7.
Data Sheet
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Register Description Register 72 UECRI/DECRI Upstream/Downstream Empty Cycle Rate Integer Part Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UECRI A2H DECRI BAH Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
MaxBurstS(3:0) Bit 7 6 5 4
Unused(1:0) 3 2
ECIntRate(9:8) 1 0
ECIntRate(7:0) MaxBurstS(3:0) Maximum Burst size for a Scheduler Block Refer to Section 4.2.2.2 "Programming the Scheduler Block Rates" on Page 106 Integer part of Empty Cycle Rate The empty cycles are required by internal logic to perform the refresh cycles of the SDRAMS. Minimum value is 10H and should be programmed during configuration.
ECIntRate(9:0)
Refer to Section 4.2.2.4 "Programming the SDRAM Refresh Empty Cell Cycles" on Page 109 for the calculation of ECIntRate and ECFracRate
Data Sheet
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Register Description Register 73 UECRF/DECRF Upstream/Downstream Empty Cycle Rate Fractional Part Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UECRF A3H DECRF BBH Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
Unused(7:0) Bit 7 6 5 4 3 2 1 0
ECFracRate(7:0)
ECFracRate(7:0) Fractional part of Empty Cycle Rate The empty cycles are required by internal logic to perform the refresh cycles of the SDRAMS. Recommended value is 00H and should be programmed during configuration. Refer to Section 4.2.2.4 "Programming the SDRAM Refresh Empty Cell Cycles" on Page 109 for the calculation of ECIntRate and ECFracRate
Data Sheet
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Register Description Register 74 UCRTQ/DCRTQ Upstream/Downstream Common Real Time Queue UTOPIA Port Select Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UCRTQ A4H DCRTQ BCH Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
Unused(9:2) Bit 7 6 5 4 3 2 1 0
Unused(1:0)
CrtqUTOPIA(5:0)
CtrqUTOPIA(5:0) Common Real Time Queue UTOPIA Port Number. Specifies one of the 48 UTOPIA ports to which the common real time queue is assigned. Only values in the range 0..47D are valid.
Data Sheet
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Register Description Register 75 USCTFM/DSCTFM Upstream/Downstream SCTF Mask Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCTFM A5H DSCTFM BDH Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
SCTFM(15:8) Bit 7 6 5 4 3 2 1 0
SCTFM(7:0) USCTFM(15:0) DSCTFM(15:0) Upstream SCTF Mask Register Downstream SCTF Mask Register USCTFM and DSCTFM control the Read or Write access from the respective transfer registers to the internal tables on a per-bit selection basis. The mask registers correspond to the respective transfer registers (USCTFT, DSCTFT): 0 The dedicated bit of the transfer register is not overwritten by the corresponding table entry bit during Read, but overwrites the table entry bit during the Write. This is a Write access to the internal table entry. The dedicated bit of the transfer register is overwritten by the corresponding table entry bit during Read and is written back to the table entry bit during Write. This is a Read access to the internal table entry.
1
Data Sheet
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Register Description Internal Table 9: Scheduler Configuration Table Fractional Transfer Registers The Scheduler Configuration Table Fractional Transfer Registers are used to access the internal Upstream/Downstream Scheduler Configuration Tables Fractional Part (SCTF) containing 128 entries each. Table 7-22 and Table 7-23 summarize the registers. Table 7-22 15 Registers SCTF Upstream Table Access 0 RAM Select: 15 MAR=17H Entry Select: 15 USCTFM Table 7-23 15 0 15 WAR (0..127 D) 0 0
SCTF RAM Entry (Upstream) 15 USCTFT 0
Registers SCTF Downstream Table Access 0 RAM Select: 15 MAR=1FH Entry Select: 0 15 WAR (0..127 D) 0 0
SCTF RAM Entry (Downstream) 15 DSCTFT 15 DSCTFM 0
SCTFU and SCTFD are transfer registers for one 16-bit SCTF upstream/downstream table entry. The upstream and downstream Scheduler Blocks use different tables (internal RAM) addressed via the MAR. The Scheduler Block number representing the table entry which needs to be read or written must be written to the WAR (Word Address Register). The dedicated SCTFU/D table entry is read into the SCTFU/D registers or modified by the SCTFU/D register value with a write mechanism. The associated mask registers, SMSKU and SMSKD, allow a bit-wise Write operation (0 - unmasked, 1 masked). In case of Read operation, the dedicated SCTFU/D register bit will be overwritten by the respective SCTFU/D table entry bit value. In case of Write operation, the dedicated SCTFU/D register bit will modify the value of the respective SCTFU/D table entry bit.
Data Sheet
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Register Description The Read or Write process is controlled by the MAR (Memory Address Register). The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to select the SCTF Upstream table, bit field MAR(4:0) must be set to 17H and 1FH for the SCTF Downstream table respectively. Bit 5 of MAR starts the transfer and is automatically cleared after execution. Table 7-24 Bit 15 WAR Register Mapping for SCTFU/SCTFD Table access 14 13 12 11 10 9 8
Unused(9:2) Bit 7 unused 6 5 4 3 SchedSel(6:0) 2 1 0
SchedSel(6:0)
Selects one of the 128 core specific Scheduler Blocks.
Data Sheet
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Register Description Register 76 USCTFT/DSCTFT Upstream/Downstream SCTF Transfer Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCTFT A6H DSCTFT BEH Written and Read by CPU to maintain the SCTF tables 14 13 12 Init(7:0) Bit 7 6 5 4 3 2 1 0 11 10 9 8
FracRate(7:0) Init(7:0) Scheduler Block Initialization Value This bit field must be written to 00H at the time of Scheduler configuration/initialization and should not be written during normal operation. Fractional Rate This value determines the fractional part of the Scheduler Block output rate. Refer to Section 4.2.2.2 "Programming the Scheduler Block Rates" on Page 106 for the calculation of FracRate
FracRate(7:0)
Note: Recommendation for changing the UTOPIA port number or scheduler rate during operation: Disable specific scheduler by read-modify-write operation to corresponding bit in registers USCEN0/DSCEN0... USCEN7/DSCEN7. Modify scheduler specific UTOPIA port number and rates via Table 8 "Scheduler Configuration Table Integer Transfer Registers" on Page 257, registers USCTI/DSCTI and Table 9 "Scheduler Configuration Table Fractional Transfer Registers" on Page 267, registers USCTFT/DSCTFT. Enable specific scheduler by read-modify-write operation to corresponding bit in registers USCEN0/DSCEN0... USCEN7/DSCEN7.
Data Sheet
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Register Description
7.2.19
Scheduler Block Enable Registers
Register 77 USCEN0/DSCEN0 Upstream/Downstream Scheduler Block Enable 0 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN0 A8H DSCEN0 C0H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(15:8) Bit 7 6 5 4 3 2 1 0
SchedEn(7:0) SchedEn(15:0) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (15..0): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 78 USCEN1/DSCEN1 Upstream/Downstream Scheduler Block Enable 1 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN0 A9H DSCEN0 C1H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(31:24) Bit 7 6 5 4 3 2 1 0
SchedEn(23:16) SchedEn(31:16) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (31..16): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 79 USCEN2/DSCEN2 Upstream/Downstream Scheduler Block Enable 2 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN2 AA H DSCEN2 C2H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(47:40) Bit 7 6 5 4 3 2 1 0
SchedEn(39:32) SchedEn(47:32) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (47..32): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 80 USCEN3/DSCEN3 Upstream/Downstream Scheduler Block Enable 3 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN3 AB H DSCEN3 C3H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(63:56) Bit 7 6 5 4 3 2 1 0
SchedEn(55:48) SchedEn(63:48) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (63..48): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 81 USCEN4/DSCEN4 Upstream/Downstream Scheduler Block Enable 4 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN4 AC H DSCEN4 C4H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(79:72) Bit 7 6 5 4 3 2 1 0
SchedEn(71:64) SchedEn(79:64) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (79..64): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 82 USCEN5/DSCEN5 Upstream/Downstream Scheduler Block Enable 5 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN5 AD H DSCEN5 C5H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(95:88) Bit 7 6 5 4 3 2 1 0
SchedEn(87:80) SchedEn(95:80) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (95..80): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 83 USCEN6/DSCEN6 Upstream/Downstream Scheduler Block Enable 6 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN6 AEH DSCEN6 C6H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(111:104) Bit 7 6 5 4 3 2 1 0
SchedEn(103:96) SchedEn (111:96) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (111..96): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description Register 84 USCEN7/DSCEN7 Upstream/Downstream Scheduler Block Enable 7 Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H USCEN7 AFH DSCEN7 C7H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
SchedEn(127:120) Bit 7 6 5 4 3 2 1 0
SchedEn(119:112) SchedEn (127:112) Scheduler Block Enable Each bit position enables/disables the respective Scheduler Block (127..112): 1 0 Scheduler Block enabled Scheduler Block disabled
Data Sheet
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Register Description
7.2.20
Common Real Time Queue Rate Registers
Register 85 UCRTRI/DCRTRI Upstream/Downstream CRT Rate Integer Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UCRTRI B0H DCRTRI C8H Written by CPU for global Scheduler configuration 14 13 12 11 10 9 8
Unused(5:0) Bit 7 6 5 4 3 2
CRTIntRate(9:8) 1 0
CRTIntRate(7:0) CRTIntRate(9:0) Integer part of CRT Queue Rate
Refer to Section 4.2.2.3 "Programming the Common Real-Time Bypass" on Page 109 for the calculation of CRTIntRate and CRTFracRate
Data Sheet
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Register Description Register 86 UCRTRF/DCRTRF Upstream/Downstream CRT Rate Fractional Registers CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UCRTRF B1H DCRTRF C9H Written and Read by CPU 14 13 12 Init(7:0) Bit 7 6 5 4 3 2 1 0 11 10 9 8
CRTFracRate(7:0) Init(7:0) Scheduler Initialization Value This bit field must be written to 00H at the time of Scheduler configuration/initialization and should not be written during normal operation. CRT Fractional Rate This value determines the fractional part of the CRT Queue output rate. Refer to Section 4.2.2.3 "Programming the Common RealTime Bypass" on Page 109 for the calculation of CRTIntRate and CRTFracRate
CRTFracRate (7:0)
Data Sheet
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Register Description
7.2.21
AVT Table Registers
Internal Table 10: VBR Table Transfer Registers VBR Context Table Transfer Registers are used to access the VBR Context Table (AVT). Refer to Chapter 3.5.9.1 for the RAM organization of this table. Table 7-25 provides an overview of the registers involved. Each AVT word consists of 32 bits. Table 7-25 31 AVT RAM word 15 ERCT1 15 ERCM1 0 15 ERCM0 0 15 ERCT0 0 15 0 15 MAR=0AH Entry Select: 0 WAR: EntrySel(9:0) = (0..1023 D) WordSel(2:0) = (0..7 D) Registers for AVT Table Access 0 RAM Select: 0
ERCT0 and ERCT1 are the transfer registers for one 32-bit word of the AVT table. Access to words are controlled by mask registers ERCM0/ERCM1. The context entry number and the corresponding word number representing the table word which needs to be read or written must be written to the Word Address Register (WAR). The dedicated AVT table word is read into the ERCT0/ERCT1 transfer registers or modified by the ERCT0/ERCT1 transfer register values with a write mechanism. The associated mask registers ERCM0 and ERCM1 allow a bit-wise Write operation (0 unmasked, 1 - masked). In case of Read operation, the dedicated ERCT0/ERCT1 register bit will be overwritten by the respective AVT table entry bit value. In case of Write operation, the dedicated ERCT0/ERCT1 register bit will modify the respective AVT table entry bit value. The Read or Write process is controlled by the Memory Address Register (MAR). The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be accessed; to select the AVT table bit field MAR(4:0) must be set to 08H.
Data Sheet
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Register Description Bit 5 of MAR starts the transfer and is cleared automatically after execution. Table 7-26 Bit 15 WAR Register Mapping for AVT Table Access 14 Unused(2:0) Bit 7 6 5 EntrySel(4:0) 4 3 13 12 11 10 EntrySel(9:5) 2 1 WordSel(2:0) 0 9 8
EntrySel(9:0) WordSel(2:0)
Selects one of the 1024 AVT table context entries. Selects one of the 8 DWORDs per AVT table context entries.
Data Sheet
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Register Description Register 87 ERCT0 AVT Table Transfer Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H ERCT0 CA H Written and Read by CPU 14 13 12 11 10 9 8
Word0(15:8) Bit 7 6 5 4 3 2 1 0
Word0(7:0)
Word0(15:0)
The meaning of the 'Word0' depends on: - The selected context entry word (WordSel(2:0)) - The mode of this particular context entry For detailed description of the context entry fields refer to "AVT Context RAM Organization and Addressing" on Page 95 f.
Data Sheet
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Register Description Register 88 ERCT1 AVT Table Transfer Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H ERCT1 CB H Written and Read by CPU 14 13 12 11 10 9 8
Word1(31:24) Bit 7 6 5 4 3 2 1 0
Word1(23:16)
Word1(31:16)
The meaning of the 'Word1' depends on - The selected context entry word (WordSel(2:0)) - The mode of this particular context entry For detailed description of the context entry fields refer to "AVT Context RAM Organization and Addressing" on Page 95 f.
Data Sheet
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Register Description Register 89 ERCM0 AVT Table Access Mask Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H ERCM0 CC H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
ERCM0(15:8) Bit 7 6 5 4 3 2 1 0
ERCM0(7:0)
ERCM0(15:0)
ERC Mask Register 0 ERC Mask Registers 0..1 control the Write access from transfer registers ERCT0 and ERCT1 to the internal AVT table on a per-bit selection basis. The mask register bit positions correspond to the respective transfer registers ERCT0 and ERCT1: 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
Data Sheet
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Register Description Register 90 ERCM1 AVT Table Access Mask Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H ERCM0 CD H Written by CPU to control internal table Read/Write access 14 13 12 11 10 9 8
Bit
15
ERCM1(31:24) Bit 7 6 5 4 3 2 1 0
ERCM1(23:16)
ERCM1(31:16)
ERC Mask Register 1 ERC Mask Registers 0..1 control the Write access from transfer registers ERCT0 and ERCT1 to the internal AVT table on a per-bit selection basis. The mask register bit positions correspond to the respective transfer registers ERCT0 and ERCT1: 0 The dedicated bit of the transfer register overwrites the table entry during Write. Does not affect Read access. The dedicated bit of the transfer register does not overwrite the table entry during Write. Does not affect Read access.
1
Data Sheet
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Register Description Register 91 ERCCONF0 ERC Configuration Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 unused Bit 7
unused
Read/Write 0061H ERCCONF0 D5H Written and Read by CPU 14 13 12 11 10 unused 3 SCANP(6:0) 2 9 unused 1 8 SCAND 0
unused(3:0) 6 5 4
SCAND
SCAN Disable
0 1 SCANP(6:0)
SCAN enabled SCAN disabled
SCAN Period Refer to "Scan Unit" on Page 90 for a description
Data Sheet
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Register Description
7.2.22
PLL Control Registers
Register 92 PLL1CONF PLL1 Configuration Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H PLL1CONF D7H Written and Read by CPU 14 13 12 11 PU1 10 RES1 9 M1(3:2) 8
Locked1 Div2En1 Div1En1 BYPAS S1 Bit 7 M1(1:0) 6 5 4
3 N1(5:0)
2
1
0
DPLL1 generates a clock that is an alternative clock source for the ABM-3G. The DPLL1 is fed by clock input signal `SYSCLK'. Signal `SYSCLKSEL' determines the clock source of the ABM-3G. Section 3.2.5 "Clocking System" on Page 52 provides the details. Locked1 DPLL1 Locked (read only) 1 0 Div2En1 DPLL1 is locked based on the current parameter setting. DPLL1 is in transient status.
Division Factor 2 Enable for DPLL1 This bit enables one of the additional divide by 2 factors subsequent to the DPLL1 output. 0 1 Division Factor 2 disabled. Division Factor 2 enabled.
Div1En1
Division Factor 1 Enable for DPLL1 This bit enables one of the additional divide by 2 factors subsequent to the DPLL1 output.
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Register Description 0 1 BYPASS1 Division Factor 1 disabled. Division Factor 1 enabled.
DPLL1 Bypass Switching between bypass and non-bypass mode is glitch-free with respect to the internal clock output. The DPLL1 is bypassed after power-on reset and can be switched to non-bypass mode by software during device configuration. 0 1 DPLL1 is internally bypassed, i.e. DPLL1 clock input connected to DPLL1 clock output DPLL1 is not bypassed, i.e. DPLL1 clock output is generated by DPLL1 depending on its parameter configuration DPLL1 is in power-down mode. (The analog part of DPLL1 is switched-off for power saving.) DPLL1 is in power on (operational) mode. DPLL1 is in operational mode. DPLL1 is in reset mode. Note: The result of reset mode is identical to bypass mode, but switching between reset and non-reset status is not glitch-free with respect to the internal clock output.
PU1
Power Up DPLL1 0
1 RES1 0 1
Reset DPLL1
M1(3:0)
M1 Parameter of DPLL1 This parameter determines the first stage division factor of DPLL1. The effective division factor is (M1 + 1) in the range 1..16. N1 Parameter of DPLL1 This parameter determines the second stage multiplication factor of DPLL1. The effective multiplication factor is (N1 + 1) in the range 1..64.
N1(5:0)
Data Sheet
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Register Description Register 93 PLLTST PLL Test Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H PLLTST D9H Written and Read by CPU 14 13 12 11 10 9 8
Reserved(15:8) Bit 7 6 5 4 3 2 1 0
Reserved(7:0)
Data Sheet
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Register Description
7.2.23
External RAM Test Registers
Register 94 EXTRAMD0 External RAM Test Data Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H EXTRAMD0 DC H Written and Read by CPU 14 13 12 11 10 9 8
Data(31:24) Bit 7 6 5 4 3 2 1 0
Data(23:16)
Data(31:16)
Upper part of data to be read from or to be written to the external RAM Note: Only the lower 20 bits of each Cell Pointer RAM entry can be accessed. Read access to the upper bits will always return 0.
Data Sheet
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Register Description Register 95 EXTRAMD1 External RAM Test Data Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 14 Read/Write 0000 H EXTRAMD1 DD H Written and Read by CPU 13 12 11 Data(15:8) Bit 7 6 5 4 3 Data(7:0) 2 1 0 10 9 8
Data(15:0)
Lower part of data to be read from or to be written to the external RAM
Data Sheet
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Register Description Register 96 EXTRAMA0 External RAM Test Address Register Low CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H EXTRAMA0 DEH Written and Read by CPU 14 13 12 11 10 9 8
Address(15:8) Bit 7 6 5 4 3 2 1 0
Address(7:0)
Address(15:0)
Lower bits of the Address The Address field selects an entry within the external RAM, selected by the EXTRAMC register. The range depends on the size of the selected external RAM (see Table 7-27).
Table 7-27 RAM Type SSRAM SSRAM SSRAM SSRAM SDRAM SDRAM SDRAM
Extended RAM Address Range for Test Access Size 64 k x 32 bit 128 k x 32 bit 256 k x 32 bit 512 k x 32 bit 32 Mbit per core 64 Mbit per core 128 Mbit per core Address Range 0 .. 65536 0 .. 131072 0 .. 262144 0 .. 524288 0 .. 1048576 0 .. 2097152 0 .. 4194304
Data Sheet
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Register Description Register 97 EXTRAMA1 External RAM Test Address Register High CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H EXTRAMA0 DFH Written and Read by CPU 14 13 12 11 10 9 8
Unused(11:4) Bit 7 6 5 4 3 2 1 0
Unused(3:0)
Address(19:16)
Address(19:16)
Upper bits of the Address The Address field selects an entry within the external RAM, selected by the EXTRAMC register. The range depends on the size of the selected external RAM (see Table 7-27).
Data Sheet
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Register Description Register 98 EXTRAMC External RAM Test Command Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H EXTRAMA0 E0H Written and Read by CPU 14 13 12 11 10 9 8
Unused(13:2) Bit 7 6 5 4 3 2 1 CPRW 0 CPRR
Unused(1:0)
CSRDW CSRDR CSRUW CSRUR
Setting a command bit starts the Read or Write procedure from/to the selected external RAM. The corresponding bit is automatically cleared after completion of the Read/Write procedure. The address to be read or to be written is provided in registers EXTRAMA0 and EXTRAMA1. The 32-bit wide data is transferred via registers EXTRAMD0 and EXTRAMD1. Note: Access to external RAM is only allowed before first cell flow. CSRDW CSRDR CSRUW CSRUR CPRW CPRR Cell Storage RAM downstream write Cell Storage RAM downstream read Cell Storage RAM upstream write Cell Storage RAM upstream read Cell Pointer RAM write Cell Pointer RAM read
Data Sheet
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Register Description
7.2.24
ABM-3G Version Code Registers
Register 99 VERL Version Number Low Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read F083 H VERL E1H Read by CPU to determine device version number 14 13 12 11 10 9 8
VERL(15..8) Bit 7 6 5 4 3 2 1 0
VERL(7..0)
*
VERL(15..0)
F083H
Data Sheet
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Register Description Register 100 VERH Version Number High Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read 1007 H VERH E2H Read by CPU to determine device version number 14 13 12 11 10 9 8
VERH(15..8) Bit 7 6 5 4 3 2 1 0
VERH(7..0)
VERH(15..0)
1007H
Data Sheet
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Register Description
7.2.25
Interrupt Status/Mask Registers
Register 101 ISRU Interrupt Status Register Upstream CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H ISRU E3H Read by CPU to evaluate interrupt events related to the upstream core. Interrupt indications must be cleared by writing a 1 to the respective bit locations; writing a 0 has no effect; 14 BCFGE 13 QIDINV 12 BUFER 1 4
AAL5 COL
Bit
15 Unused
11 LCI INVAL 3
10
9
8 BUFER 2 0 reserve d
PARITY SOCER ER 2 1 BUFER 4
Bit
7 BUFER 3
6
5
CDVOV MUXOV
RMCER BIP8ER
BCFGE QIDINV
Buffer Configuration Error upstream This interrupt is generated if the ABM-3G tries to write a cell into a disabled queue. The cell is discarded in this case. (Typically occurs on queue configuration errors.) Unexpected buffer error number 1. Should never occur in normal operation. Immediate reset of the chip recommended. Error when performing the internal address reduction The cell is discarded. Parity error at UTOPIA Receive Upstream (PHY) Interface detected.
BUFER1
LCIINVAL
PARITYER
Data Sheet
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Register Description SOCER Start of Cell Error at UTOPIA Receive Upstream (PHY) Interface detected. Unexpected Buffer Error number 2. Should never occur in normal operation. Immediate reset of the chip is recommended. Unexpected Buffer Error number 3. Should never occur in normal operation. Immediate reset of the chip is recommended. The maximum upstream CDV value for shaped connections given in CDVU register has been exceeded. This interrupt is a notification only; that is, no cells are discarded due to this event. Indicates that a Scheduler Block lost a serving time slot. (Can indicate a static backpressure on one port). The 'MUXOV' interrupt is generated when the number of lost serving time slots exceeds the number specified in bit field MaxBurstS(3:0) (see register UECRI/DECRI). No further action is required upon this interrupt. Indicates that an interrupt event occurred in the upstream AAL5 unit. The interrupt reason must be read from the AAL5 status register "UA5SARS/DA5SARS" on Page 172 (upstream). RM Cell received with corrupted CRC-10. BIP-8 error detected when reading a cell from the upstream external SDRAM. BIP-8 protects the cell header of each cell. The cell is discarded. One single sporadic event can be ignored. Hardware should be taken out of service when the error rate exceeds 10-10.
BUFER2
BUFER3
CDVOV
MUXOV
AAL5COL
RMCER BIP8ER
Data Sheet
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Register Description BUFER4 Unexpected Buffer Error number 4. Should never occur in normal operation. Immediate reset of the chip recommended. For consistency check the ABM-3G stores the queue ID with each cell written to the respective queue within the cell storage RAM. When reading a cell from the cell storage RAM, the queue ID is compared to the stored queue ID. A queue ID mismatch would indicate a global buffering/pointer problem.
Note: Several mechanisms are implemented in the ABM-3G to check for consistency of pointer operation and internal/external memory control. The interrupt events BUFER1..BUFER4 indicate errors detected by these mechanisms. It is recommended that these interrupts be classified as "fatal device errors."
Data Sheet
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Register Description Register 102 ISRD Interrupt Status Register Downstream CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H ISRD E4H Read by CPU to evaluate interrupt events related to the downstream core. Interrupt indications must be cleared by writing a 1 to the respective bit locations; writing a 0 has no effect; 14 BCFGE 13 QIDINV 12 BUFER 1 4
AAL5 COL
Bit
15 Unused
11 LCI INVAL 3
10
9
8 BUFER 2 0 reserve d
PARITY SOCER ER 2 1 BUFER 4
Bit
7 BUFER 3
6
5
CDVOV MUXOV
RMCER BIP8ER
BCFGE QIDINV
Buffer Configuration Error downstream This interrupt is generated if the ABM-3G tries to Write a cell into a disabled queue. The cell is discarded. (Typically occurs on queue configuration errors.) Unexpected Buffer Error number 1. Should never occur in normal operation. Immediate reset of the chip is recommended. Error when performing the internal address reduction The cell is discarded. Parity Error at UTOPIA Receive Downstream (PHY) Interface detected. Start of Cell Error at UTOPIA Receive Downstream (PHY) Interface detected.
BUFER1
LCIINVAL
PARITYER
SOCER
Data Sheet
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Register Description
BUFER2
Unexpected Buffer Error number 2. Should never occur in normal operation. Immediate reset of the chip is recommended. Unexpected Buffer Error number 3. Should never occur in normal operation. Immediate reset of the chip recommended. The maximum downstream CDV value for shaped connections given in CDVU register has been exceeded. This interrupt is a notification only; that is, no cells are discarded due to this event. Indicates that a Scheduler Block lost a serving time slot. (Can indicate a static backpressure on one port). The 'MUXOV' interrupt is generated when the number of lost serving time slots exceeds the number specified in bit field MaxBurstS(3:0) (see register UECRI/DECRI). No further action is required upon this interrupt. Indicates that an interrupt event occurred in the downstream AAL5 unit. The interrupt reason must be read from the AAL5 status register "UA5SARS/DA5SARS" on Page 172 (downstream). RM cell received with corrupted CRC-10. BIP-8 error detected when reading a cell from the downstream external SDRAM. BIP-8 protects the cell header of each cell. The cell is discarded. One single sporadic event can be ignored. Hardware should be taken out of service when the error rate exceeds 10-10.
BUFER3
CDVOV
MUXOV
AAL5COL
RMCER BIP8ER
Data Sheet
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Register Description BUFER4 Unexpected Buffer Error number 4. Should never occur in normal operation. Immediate reset of the chip is recommended. For consistency check the ABM-3G stores the queue ID with each cell written to the respective queue within the cell storage RAM. When reading a cell from the cell storage RAM, the queue ID is compared to the stored queue ID. A queue ID mismatch would indicate a global buffering/pointer problem.
Note: Several mechanisms are implemented in the ABM-3G to check for consistency of pointer operation and internal/external memory control. The interrupt events BUFER1..BUFER4 indicate errors detected by these mechanisms. It is recommended that these interrupts be classified as "fatal device errors."
Data Sheet
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Register Description Register 103 ISRC Interrupt Status Register Common CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H ISRC E5H Read by CPU to evaluate interrupt events related to both cores. Interrupt indications must be cleared by writing a 1 to the respective bit locations; writing a 0 has no effect; 14 13 12 11 10 9 8
Bit
15
Unused(10:3) Bit 7 6 Unused(2:0) 5 4 3 2 1
DQ VCMGD
0
UQ VCMGD
RAMER DDQRD UDQRD
RAMER
Configuration of common Cell Pointer RAM has been changed after cells have been received (see Register MODE1, bit field CPR). Downstream Dummy Queue Relogged/Deactivated This interrupt confirms the dummy queue operation being activated and deactivated. (see Register 38: QCT1) Upstream Dummy Queue Relogged/Deactivated This interrupt confirms the dummy queue operation being activated and deactivated. (see Register 38: QCT1) Downstream Queue VC-Merge Group Deactivated This interrupt confirms the VC-Merge group being deactivated. Upstream Queue VC-Merge Group Deactivated This interrupt confirms the VC-Merge group being deactivated.
DDQRD
UDQRD
DQVCMGD
UQVCMGD
Data Sheet
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Register Description Register 104 IMRU Interrupt Mask Register Upstream CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H IMRU E6H Written by CPU to control interrupt signal effective events 14 13 12 11 10 9 8
Bit
15
IMRU(15:8) Bit 7 6 5 4 3 2 1 0
IMRU(7:0) IMRU(15:0) Interrupt Mask Upstream Each bit controls whether the corresponding interrupt indication in register ISRU (same bit location) activates the interrupt signal: 1 0 Interrupt indication masked. The interrupt signal is not activated upon this event. Interrupt indication unmasked. The interrupt signal is activated upon this event.
Data Sheet
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Register Description Register 105 IMRD Interrupt Mask Register Downstream CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H IMRD E7H Written by CPU to control interrupt signal effective events 14 13 12 11 10 9 8
Bit
15
IMRD(15:8) Bit 7 6 5 4 3 2 1 0
IMRD(7:0) IMRD(15:0) Interrupt Mask Downstream Each bit controls whether the corresponding interrupt indication in register ISRD (same bit location) activates the interrupt signal: 1 0 Interrupt indication masked. The interrupt signal is not activated upon this event. Interrupt indication unmasked. The interrupt signal is activated upon this event.
Data Sheet
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Register Description Register 106 IMRC Interrupt Mask Register Common CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H IMRC E8H Written by CPU to control interrupt signal effective events 14 13 12 11 10 9 8
Bit
15
IMRC(15:8) Bit 7 6 5 4 3 2 1 0
IMRC(7:0) IMRC(15:0) Interrupt Mask Common Each bit controls whether the corresponding interrupt indication in register ISRC (same bit location) activates the interrupt signal: 1 0 Interrupt indication masked. The interrupt signal is not activated upon this event. Interrupt indication unmasked. The interrupt signal is activated upon this event.
Data Sheet
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Register Description
7.2.26
RAM Select Registers
Register 107 MAR Memory Address Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H MAR EBH Written by CPU to address internal RAM/tables for Read or Write operation via transfer registers 14 13 12 11 10 9 8
Bit
15
Unused(9:2) Bit 7 6 5 Start_R 4 3 2 MAR(4:0) 1 0
Unused Start_W Start_W
This command bit starts the Write procedure to the internal RAM/ table addressed by bit field MAR(4:0). The specific data transfer and mask registers must be prepared appropriately in advance. This bit is automatically cleared after completion of the Write procedure. Simplifies Read access without need to touch the mask registers Memory Address This bit field selects one of the internal RAM/tables for Read or Write operation: 00000 00001 00010 00011 00111 01010 10000 LCI: LCI Table RAM (see page 191) TCT: Traffic Class Table (see page 195) QCT: Queue Configuration Table (see page 211) SBOC: Scheduler Block Occupation Table (see page 223) MGT: Merge Group Table (see page 230) AVT: VBR Table (see page 280) QPT1 Upstream: Queue Parameter Table 1 Up (see page 247)
Start_R MAR(4:0)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description 10001 11000 11001 10111 QPT2 Upstream: Queue Parameter Table 2 Up (see page 251) QPT1 Downstream: Queue Parameter Table 1 Dn (see page 247) QPT2 Downstream: Queue Parameter Table 2 Dn (see page 251) SCTF Upstream: Scheduler Configuration Table Fractional Part (see page 257) SCTF Downstream: Scheduler Configuration Table Fractional Part (see page 267)
11111
Note: The SCTI Table (Scheduler Configuration Table Integer Part) is addressed via dedicated address registers and thus not listed in bit field MAR(4:0) (see page 259). Note: MAR(4:0) values not listed above are invalid and reserved. It is recommended to not use invalid/reserved values.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 108 WAR Word Address Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Read/Write 0000 H WAR ECH Written by CPU to address entries of internal RAM/ tables for Read or Write operation via transfer registers. 14 13 12 11 10 9 8
Bit
15
WAR(15:8) Bit 7 6 5 4 3 2 1 0
WAR(7:0) WAR(15:0) Word Address This bit field selects an entry within the internal RAM/table selected by the MAR register. In general, it can address up to 64K entries. The current range of supported values depends on the size and organization of the selected RAM/table. Thus, the specific WAR register meaning is listed in the overview part of each internal RAM/table description: LCI TCT QCT SBOC QPTHU QPTHD QPTLU QPTLD LCI Table RAM (see page 191) Traffic Class Table (see page 195) Queue Configuration Table (see page 223) Scheduler Block Occupation Table (see page 223) QPT High Word Upstream: Queue Parameter Table (see page 247f.) QPT High Word Downstream: Queue Parameter Table (see page 247f.) QPT Low Word Upstream: Queue Parameter Table(see page 247) QPT Low Word Downstream: Queue Parameter Table (see page 247)
Data Sheet
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Register Description SCTFU SCTF Upstream: Scheduler Configuration Table Fractional Part (see page 267) SCTF Downstream: Scheduler Configuration Table Fractional Part (see page 267)
SCTFD
Note: The SCTI Table (Scheduler Configuration Table Integer Part) is addressed via dedicated address registers and, thus, is not listed in the MAR and WAR registers (see page 257).
Data Sheet
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Register Description
7.2.27
Global ABM-3G Status and Mode Registers
Register 109 USTATUS ABM-3G UTOPIA Status Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 unused Bit 7 unused DUTFL(6:0) 6 5 4 Read/Write 0000 H USTATUS Read by CPU 14 13 12 11 DUTFL(6:0) 3 UUTFL(6:0) Downstream UTOPIA Receive Buffer Fill Level This bit field indicates the current number of cells stored in the UTOPIA receive buffers (0..64 cells). 2 1 0 10 9 8 EDH
UUTFL(6:0)
Upstream UTOPIA Receive Buffer Fill Level This bit field indicates the current number of cells stored in the UTOPIA receive buffer (0..64 cells).
Data Sheet
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Register Description Register 110 MODE1 ABM-3G Mode 1 Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 SWRES Read/Write 0000 H MODE1 EEH Written and Read by CPU 14
0
13
12
11 VC MERGE 3 CRC10
10 INIT RAM 2 LCItog
9 INIT SDRAM 1
8 CORE
CPR(1:0)
Bit
7 WGS
6 0
5 0
4 BIP8
0
LCIMOD(1:0)
SWRES
Software Reset (clears automatically after four cycles). This bit is automatically cleared after execution. 'SWRES' controls reset of all ABM-3G units. 1 (0) Starts internal reset procedure self-clearing
CPR(1:0)
Cell Pointer Ram Size configuration (see also Table 7-3 "External RAM Sizes" on Page 177) 00 01 10 11 256k pointer entries per direction (corresponds to 256k cells in each cell storage RAM) 128k pointer entries per direction (corresponds to 128k cells in each cell storage RAM) 64k pointer entries per direction (corresponds to 64k cells in each cell storage RAM) reserved
Note: The Cell Pointer RAM Size should be programmed during initialization and should not be changed during operation.
Data Sheet
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Register Description VCMerge VC Merge Enable This bit enables VC-Merge operation on a global basis. It determines the usage (required width) of the Cell Pointer RAM, since VC-Merge operation requires one additional flag `EOP Mark' in the CPR. (see also Table 5-10 "SSRAM Configuration Examples" on Page 139) 0 1 INITRAM VC-Merge operation disabled. VC-Merge operation enabled.
Init RAM Start of Initialization of the internal RAM. This bit is automatically cleared after execution. 1 Starts internal RAM initialization procedure. Note: The internal RAM initialization process can be activated only once after hardware reset. (0) self-clearing
INITSDRAM
Init SDRAM Initialization and configuration of the external SDRAM. This bit must be set to 1 after reset (initial pause of at least 200 s is necessary) and is automatically cleared by the ABM-3G after configuration of the SDRAM has been executed. 1 (0) Starts SDRAM initialization procedure self-clearing
CORE
Downstream Core Disable This bit disables the downstream ABM-3G Core, which is necessary in some MiniSwitch configurations (Uni-Directional Mode using one core). It is recommended to set CORE = 0 in Bi-directional operation modes. 1 0 Downstream ABM-3G core disabled Downstream ABM-3G core enabled
WGS
Work Group Switch Mode Selects MiniSwitch (Uni-directional) Mode if set to 1.
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Data Sheet
ABM-3G PXF 4333 V1.1
Register Description 1 MiniSwitch (Uni-directional) operation mode selected: upstream transmit UTOPIA Interface is disabled; downstream receive UTOPIA Interface is disabled. Normal (Bi-directional) operation mode
0 BIP8
Disables discard of cells with BIP-8 header error. 1 0 BIP-8 errored cells are not discarded BIP-8 errored cells are discarded
CRC10
Disables discard of RM cells with defect CRC10. 1 0 CRC10 errored RM cells are not discarded CRC10 errored RM cells are discarded
LCItog
Enables toggling of the LCI(0) bit in outgoing cells in MiniSwitch (uni-directional) mode. 1 0 LCI bit 0 is toggled in outgoing cells in case of MiniSwitch operation mode selected LCI bit 0 remains unchanged
Note: Does not affect the cell header if Internal Address Reduction is used. LCIMOD(1:0) Specifies the expected mapping of Local Connection Identifier (LCI) field to cell header: 00 01 10 LCI(13, 12) ='00', LCI(11:0) mapped to VPI(11:0) field LCI(15:0) mapped to VCI(15:0) field; LCI(15:14) mapped to UDF1(1:0) field; LCI(13:12) mapped to UDF1(7:6) field; LCI(11:0) mapped to VPI(11:0) field Internal Address reduction mode; The LCI is derived from programmable parts of the VPI, VCI and PN bit fields. The derived LCI is used by the ABM-3G, but nor written to the cell.
11
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 111 MODE2 ABM-3G Mode 2 Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 SD CAW Bit 7 PNSRC SDCAW Read/Write 0800H MODE EFH Written and Read by CPU 14 SDRR 13 unused 12 1 11 TUTS 10 DQSC 9 QS(1:0) 8
6
5
4
3
2
1 PNUM(2:0)
0
MNUM(3:0) SDRAM Column Address Width 0 1 8 bit 9 bit
SDRR
SDRAM Refresh Rate 0 1 Default Refresh Rate (4096 cycles/s) Double Refresh Rate (8192 cycles/s)
TUTS
Tristate all UTOPIA Signals 0 1 Normal mode UTOPIA Signals in Tristate mode
DQSC
Disable Quarter Segment Check 0 1 Normal mode Quarter Segment Check disabled
QS(1:0)
Quarter Segment
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description If Quarter Segment Check is enabled, the ABM-3G processes only cells matching the LCI segment: LCI(15:14) = QS(1:0) All other cells are forwarded depending on the value found in entry 0 of the LCT table. Default: send to the Common Real-Time Queue to be processed by a subsequent ABM-3G (cascading). PNSRC Port Number Source This bit determines which Port Number field is used for internal Address Reduction Mode: 0 1 MNUM(3:0) PN field is taken from the UTOPIA Port number, that accepted the cell. PN field is taken from the UDF1(5:0) field of the cell
M Parameter This bit field determines the ranges of VPI and VCI cell header fields mapped into the LCI in internal Address Reduction mode. Chapter 3.2.4 provides the details. P Parameter This bit field determines the number of port number bits mapped into the LCI in internal Address Reduction mode. Chapter 3.2.4 provides the details.
PNUM(2:0)
Data Sheet
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Register Description
7.2.28
UTOPIA Configuration Registers
Register 112 UTRXCFG Upstream/Downstream UTOPIA Receive Configuration Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 DURD Read/Write 0001 H UTRXCFG F0H Written and Read by CPU 14 DURUT 13 DURPD 12 DURPE 11 10 9 DURBU S 1 UURBU S 8 DURM
DURCFG(1:0)
Bit
7 UURD
6 UURUT
5 UURPD
4 UURPE
3
2
0 UURM
UURCFG(1:0)
*
DURD UURD
Downstream UTOPIA Receive Discard Upstream UTOPIA Receive Discard 0 1 Normal operation Discard all cells without notification
DURUT UURUT
Downstream UTOPIA Receive UDF2 Transparent Upstream UTOPIA Receive UDF2 Transparent 0 1 PN mapped to UDF2 (for internal processing) UDF2 transparent (BIP8 checksum not usable)
DURPD UURPD
Downstream UTOPIA Receive Parity Error discard Upstream UTOPIA Receive Parity Error discard 0 No discarding of cells with Parity Error
Data Sheet
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Register Description 1 DURPE UURPE Discarding of cells with Parity Error
Downstream UTOPIA Receive Parity Check Enable Upstream UTOPIA Receive Parity Check Enable 0 1 Parity check disabled Parity check enabled
DURCFG(1:0) UURCFG(1:0)
Downstream UTOPIA Receive Port Configuration Upstream UTOPIA Receive Port Configuration 00 01 10 11 4 x 12 ports 4 x 12 ports 4 x 12 ports Level 1 Mode (4 x 1 port)
DURBUS UURBUS
Downstream UTOPIA Receive Bus Width Upstream UTOPIA Receive Bus Width 0 1 8-bit bus width 16-bit bus width
DURM UURM
Downstream UTOPIA Receive Mode Upstream UTOPIA Receive Mode 0 1 Slave Mode Master Mode
Data Sheet
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Register Description Register 113 UUTRXP0 Upstream UTOPIA Receive Port Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTRXP0 F1H Written and Read by CPU 14 13 12 11 10 9 8
UURXPEnable(15..8) Bit 7 6 5 4 3 2 1 0
UUTRXPEnable(7..0)
*
UUTRXPEnable (15:0)
Upstream UTOPIA Receive Port Enable Each bit enables or disables the respective UTOPIA port (15..0): bit = 0 bit = 1 Port disabled. Port enabled.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 114 UUTRXP1 Upstream UTOPIA Receive Port Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTRXP1 F2H Written and Read by CPU 14 13 12 11 10 9 8
UURXPEnable(31..24) Bit 7 6 5 4 3 2 1 0
UUTRXPEnable(23..16)
*
UUTRXPEnable (31:16)
Upstream UTOPIA Receive Port Enable Each bit enables or disables the respective UTOPIA port (31..16): bit = 0 bit = 1 Port disabled. Port enabled.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 115 UUTRXP2 Upstream UTOPIA Receive Port Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTRXP2 F3H Written and Read by CPU 14 13 12 11 10 9 8
UURXPEnable(47..40) Bit 7 6 5 4 3 2 1 0
UUTRXPEnable(39..32)
*
UUTRXPEnable (47:32)
Upstream UTOPIA Receive Port Enable Each bit enables or disables the respective UTOPIA port (47..32): bit = 0 bit = 1 Port disabled. Port enabled.
Data Sheet
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Register Description Register 116 DUTRXP0 Downstream UTOPIA Receive Port Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H DUTRXP0 F4H Written and Read by CPU 14 13 12 11 10 9 8
DURXPEnable(15..8) Bit 7 6 5 4 3 2 1 0
DUTRXPEnable(7..0)
*
DUTRXPEnable (15:0)
Downstream UTOPIA Receive Port Enable Each bit enables or disables the respective UTOPIA port (15..0): bit = 0 bit = 1 Port disabled. Port enabled.
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 117 DUTRXP1 Downstream UTOPIA Receive Port Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H DUTRXP1 F5H Written and Read by CPU 14 13 12 11 10 9 8
DURXPEnable(31..24) Bit 7 6 5 4 3 2 1 0
DUTRXPEnable(23..16)
*
DUTRXPEnable (31:16)
Downstream UTOPIA Receive Port Enable Each bit enables or disables the respective UTOPIA port (31..16): bit = 0 bit = 1 Port disabled. Port enabled.
Data Sheet
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Register Description Register 118 DUTRXP2 Downstream UTOPIA Receive Port Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H DUTRXP2 F6H Written and Read by CPU 14 13 12 11 10 9 8
DURXPEnable(47..40) Bit 7 6 5 4 3 2 1 0
DUTRXPEnable(39..32)
*
DUTRXPEnable (47:32)
Downstream UTOPIA Receive Port Enable Each bit enables or disables the respective UTOPIA port (47..32): bit = 0 bit = 1 Port disabled. Port enabled.
Data Sheet
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Register Description Register 119 UUTTXCFG Upstream UTOPIA Transmit Configuration Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTTXCFG F7H Written and Read by CPU 14 unused(2:0) 13 12 UUTES 11 UUTUT 10 9 8 UUTBU S 0 UUTM
UUTCFG(1:0)
Bit
7
6
5
4 UUTQL(6:0)
3
2
1
*
UUTM
Upstream UTOPIA Transmit Mode 0 1 Slave Mode Master Mode
UUTQL(6:0)
Upstream UTOPIA Transmit Queue Length Chapter 5.2.2 provides the details. 64 cells maximum
UURBUS
Upstream UTOPIA Transmit Bus Width 0 1 8-bit bus width 16-bit bus width
UUTCFG(1:0)
Upstream UTOPIA Transmit Port Configuration 00 01 10 4 x 12 ports 4 x 12 ports 4 x 12 ports
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Data Sheet
ABM-3G PXF 4333 V1.1
Register Description 11 UUTUT Level 1 Mode (4 x 1 port)
Upstream UTOPIA Transmit UDF2 Transparent 0 1 Port number is mapped to UDF2 UDF2 not modified at transmit Interface (UDF2 transparency if set together with UTRXCFG.UURUT)
UUTES
Upstream UTOPIA Transmit Extended Slave 0 1 1x4 or 4x12 1x31 together with UUTM="0" (slave)
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 120 DUTTXCFG Downstream UTOPIA Transmit Configuration Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0001 H DUTTXCFG F8H Written and Read by CPU 14 unused(2:0) 13 12 DUTES 11 DUTUT 10 9 8 DUTBU S 0 DUTM
DUTCFG(1:0)
Bit
7
6
5
4 DUTQL(6:0)
3
2
1
*
DUTM
Downstream UTOPIA Transmit Mode 0 1 Slave Mode Master Mode
DUTQL(6:0)
Downstream UTOPIA Transmit Queue Length Chapter 5.1.2 provides the details. 64 cells maximum
DURBUS
Downstream UTOPIA Transmit Bus Width 0 1 8-bit bus width 16-bit bus width
DUTCFG(1:0)
Downstream UTOPIA Transmit Port Configuration 00 01 10 4 x 12 ports 4 x 12 ports 4 x 12 ports
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Data Sheet
ABM-3G PXF 4333 V1.1
Register Description 11 DUTUT Level 1 Mode (4 x 1 port)
Downstream UTOPIA Transmit UDF2 Transparent 0 1 Port number is mapped to UDF2 UDF2 not modified at transmit Interface (UDF2 transparency if set together with UTRXCFG.DURUT)
DUTES
Downstream UTOPIA Transmit Extended Slave 0 1 1x4 or 4x12 1x31 together with UUTM="0" (slave)
Data Sheet
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Register Description Register 121 UUTTXP0 Upstream UTOPIA Transmit Port Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTTXP0 F9H Written and Read by CPU 14 13 12 11 10 9 8
UUTXPEnable(15..8) Bit 7 6 5 4 3 2 1 0
UUTTXPEnable(7..0)
*
UUTTXPEnable (15:0)
Upstream UTOPIA Transmit Port Enable Each bit enables or disables the respective UTOPIA port (15..0): bit = 0 bit = 1 Port disabled. Port enabled.
Note: If transmit port is disabled, cells assigned to this port are discarded without notification
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 122 UUTTXP1 Upstream UTOPIA Transmit Port Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTTXP1 FAH Written and Read by CPU 14 13 12 11 10 9 8
UUTTXPEnable(31..24) Bit 7 6 5 4 3 2 1 0
UUTTXPEnable(23..16)
*
UUTTXPEnable (31:16)
Upstream UTOPIA Transmit Port Enable Each bit enables or disables the respective UTOPIA port (31..16): bit = 0 bit = 1 Port disabled. Port enabled.
Note: If transmit port is disabled, cells assigned to this port are discarded without notification
Data Sheet
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Register Description Register 123 UUTTXP2 Upstream UTOPIA Transmit Port Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H UUTTXP2 FBH Written and Read by CPU 14 13 12 11 10 9 8
UUTTXPEnable(47..40) Bit 7 6 5 4 3 2 1 0
UUTTXPEnable(39..32)
*
UUTTXPEnable (47:32)
Upstream UTOPIA Transmit Port Enable Each bit enables or disables the respective UTOPIA port (47..32): bit = 0 bit = 1 Port disabled. Port enabled.
Note: If transmit port is disabled, cells assigned to this port are discarded without notification
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 124 DUTTXP0 Downstream UTOPIA Transmit Port Register 0 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H DUTTXP0 FCH Written and Read by CPU 14 13 12 11 10 9 8
DUTTXPEnable(15..8) Bit 7 6 5 4 3 2 1 0
DUTTXPEnable(7..0)
*
DUTTXPEnable (15:0)
Downstream UTOPIA Transmit Port Enable Each bit enables or disables the respective UTOPIA port (15..0): bit = 0 bit = 1 Port disabled. Port enabled.
Note: If transmit port is disabled, cells assigned to this port are discarded without notification
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 125 DUTTXP1 Downstream UTOPIA Transmit Port Register 1 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H DUTTXP1 FDH Written and Read by CPU 14 13 12 11 10 9 8
DUTTXPEnable(31..24) Bit 7 6 5 4 3 2 1 0
DUTTXPEnable(23..16)
*
DUTTXPEnable (31:16)
Downstream UTOPIA Transmit Port Enable Each bit enables or disables the respective UTOPIA port (31..16): bit = 0 bit = 1 Port disabled. Port enabled.
Note: If transmit port is disabled, cells assigned to this port are discarded without notification
Data Sheet
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ABM-3G PXF 4333 V1.1
Register Description Register 126 DUTTXP2 Downstream UTOPIA Transmit Port Register 2 CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H DUTTXP2 FEH Written and Read by CPU 14 13 12 11 10 9 8
DUTTXPEnable(47..40) Bit 7 6 5 4 3 2 1 0
DUTTXPEnable(39..32)
*
DUTTXPEnable (47:32)
Downstream UTOPIA Transmit Port Enable Each bit enables or disables the respective UTOPIA port (47..32): bit = 0 bit = 1 Port disabled. Port enabled.
Note: If transmit port is disabled, cells assigned to this port are discarded without notification
Data Sheet
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Register Description
7.2.29
Test Registers/Special Mode Registers
Register 127 TEST TEST Register CPU Accessibility: Reset Value: Offset Address: Typical Usage: Bit 15 Read/Write 0000 H TEST FFH Written and Read by CPU for device test purposes 14 13 12 11 10 9 8
Unused(5:0) Bit 7 6 5 4 3 2
Reserved(7:6) 1 0
CLKdelay(1:0)
*
Reserved(5:0)
CLKDelay(1:0)
This bit field adjusts the delay of RAMCLK output with respect to SYSCLK input. "Test Interface" on Page 141 provides the details. 00 01 10 11 Delay 0 Delay 2 Delay 4 Delay 6
Data Sheet
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Electrical Characteristics
8
8.1
Table 8-1 Parameter
Electrical Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings Symbol Limit Values -40 to 85 -40 to 125 -0.3 to 3.6 -0.4 to VDD + 0.4 2000 Unit C C V V V
Ambient temperature under biasPXF Storage temperature IC supply voltage with respect to ground Voltage on any pin with respect to ground ESD robustness HBM: 1.5 k, 100 pF
1)
TA Tstg VDD VS
VESD,HBM
1)
According to MIL-Std 883D, method 3015.7 and ESD Association Standard EOS/ESD-5.1-1993. The RF Pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 V (versus VS or GND). The high frequency performance prohibits the use of adequate protective structures.
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
8.2
Table 8-2 Parameter
Operating Range
Operating Range Symbol Limit Values min. max. 85 125 3.0 1.62 0 3.6 1.98 0 2.5 C C V V V W -40 Unit Test Condition
Ambient temperature under bias Junction temperature Supply voltage 3.3V Supply voltage 1.8V Ground Power dissipation
TA TJ VDD33 VDD18 VSS P
Note: In the operating range, the functions given in the circuit description are fulfilled.
Data Sheet
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Electrical Characteristics
8.3
*
DC Characteristics
DC Characteristics Symbol min. Limit Values typ. max 0.8 V V V V LVTTL (3.3 V) -0.4 2.0 0.2 2.4 Unit Notes
Table 8-3 Parameter
Input low voltage Input high voltage Output low voltage Output high voltage
VIL VIH VOL VOH
VDD +
0.3 0.4
VDD
IOL = 5 mA IOH = - 5 mA all
pins except TDO (TDO: IOH = - 3 mA)
Average power supply current
ICC
(AV)
330
mA
VDD33 = 3.3 V, VDD18 = 1.8 V, TA = 25 C,
SYSCLK = 52 MHz; URXCLKU = UTXCLKU = URXCLKD = UTXCLKD = 52 MHz;
Average ICCPD power down supply current (AV)
10
mA
VDD = 3.3 V, TA = 25 C,
no output loads, no clocks
Average power dissipation
P (AV)
1
1.3
W
VDD33 = 3.3 V, VDD18 = 1.8 V, TA = 25 C,
SYSCLK = 52 MHz; URXCLKU = UTXCLKU = URXCLKD = UTXCLKD = 52 MHz;
Data Sheet
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Electrical Characteristics Table 8-3 Parameter Input current DC Characteristics (cont'd) Symbol min. Limit Values typ. max 1 8 A A -1 4 Unit Notes
IIIN
VIN = VDD33 or VSS VIN = VDD33 for
Inputs with internal PullDown resistor
-4
-8
A
VIN = VSS for
Inputs with internal Pull-Up resistor
Input leakage current
IIL
1
A
VDD33 = 3.3 V,V
DD18 = 1.8 V, GND = 0 V; all other pins are floating
Output leakage current
IOZ
1
A
VDD33 = 3.3 V,V
DD18 = 1.8 V, GND = 0 V; VOUT = 0 V
Data Sheet
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ABM-3G PXF 4333 V1.1
Electrical Characteristics
8.4
AC Characteristics
TA = -40 to 85 C, VDD33 = 3.3 V 10%, VDD18 = 1.8 V 10%, VSS = 0 V All inputs are driven to VIH = 2.4 V for a logical 1 and to VIL = 0.4 V for a logical 0 All outputs are measured at VH = 2.0 V for a logical 1 and at VL = 0.8 V for a logical 0
The AC testing input/output waveforms are shown in Figure 8-1.
*
VH Test Points VL
VH
Device under Test
VL
CLOAD = 50 pF max
Figure 8-1
Input/Output Waveform for AC Measurements
Table 8-4 Parameter
Clock Frequencies Symbol Limit Values min. max. 52 52 {fint. coreclock, 52 MHz} {fint. coreclock, 52 MHz} {fint. coreclock, 52 MHz} {fint. coreclock, 52 MHz} MHz MHz MHz 25 25 Unit
Core clock (internal) External core clock source UTOPIA clocks at PHY-side
fint.coreclock
SYSCLK UTRXCLKU
fint.coreclock/2
UTTXCLKD
fint.coreclock/2
MHz
UTOPIA clock at Backplane-side UTRXCLKD
fint.coreclock/2
MHz
UTTXCLKU
fint.coreclock/2
MHz
Clock for external RAM
RAMCLK
fint.coreclock
fint.coreclock
Data Sheet
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Electrical Characteristics
8.4.1 8.4.1.1
*
Microprocessor Interface Timing Intel Mode Microprocessor Write Cycle Timing (Intel)
MPADR
1 9
MPCS
2 8
MPWR
10 3 5 6 11
MPRDY
4 7
MPDAT
Figure 8-2 Table 8-5 No. 1 2 3 4 5 6 7 8 9 10 11
Microprocessor Interface Write Cycle Timing (Intel) Microprocessor Interface Write Cycle Timing (Intel) Limit Values Min Typ Max ns ns 20 5 SYSCLK
cycles
Parameter
Unit
MPADR setup time before MPCS low
MPCS setup time before MPWR low MPRDY low delay after MPWR low Pulse width MPRDY low MPRDY high to MPWR high MPDAT hold time after MPWR high MPCS hold time after MPWR high MPADR hold time after MPWR high MPCS low to MPRDY low impedance MPCS high to MPRDY high impedance
0 0 0 4 SYSCLK cycles 5 5 5 5 0 15
ns ns
MPDAT setup time before MPWR high 5
ns ns ns ns ns ns
Data Sheet
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Electrical Characteristics
8.4.1.2
*
Microprocessor Read Cycle Timing (Intel)
MPADR
20 28
MPCS
21 27
MPRD
31 22 23 25 32
MPRDY
29 24 26
MPDAT
30
Figure 8-3 Table 8-6 No. 20 21 22 23 24 25 26 27 28 29 30 31 32
Microprocessor Interface Read Cycle Timing (Intel) Microprocessor Interface Read Cycle Timing (Intel) Limit Values Min Typ Max ns ns 20 5 SYSCLK cycles ns ns ns ns ns 15 17 15 ns ns ns ns ns 0 0 0 4 SYSCLK cycles 5 5 2 5 5 0 0 Unit
Parameter
MPADR setup time before MPCS low
MPCS setup time before MPRD low MPRDY low delay after MPRD low Pulse width MPRDY low MPDAT valid before MPRDY high MPRDY high to MPRD high MPDAT hold time after MPRD high MPCS hold time after MPRD high MPADR hold time after MPRD high MPRD low to MPDAT low impedance MPCS low to MPRDY low impedance MPCS high to MPRDY high impedance
341
MPRD high to MPDAT high impedance 0
Data Sheet
2001-12-17
ABM-3G PXF 4333 V1.1
Electrical Characteristics
8.4.2 8.4.2.1
*
Microprocessor Interface Timing Motorola Mode Microprocessor Write Cycle Timing (Motorola)
MPADR
40 48
MPCS
41 47
(MPRD) DS
51 52
(MPWR) R/W (MPRDY) RDY (DTACK) MPDAT
53
42
44
45
54
43
46
Figure 8-4 Table 8-7 No. 40 41 42 43 44 45 46 47 48 51 52
Microprocessor Interface Write Cycle Timing (Motorola) Microprocessor Interface Write Cycle Timing (Motorola) Limit Values Min Typ Max ns ns 20 5 SYSCLK cycles ns ns ns ns ns ns ns ns 0 0 0 5 4 SYSCLK cycles 5 5 5 5 10 0 Unit
Parameter
MPADR setup time before MPCS low
MPCS setup time before DS low RDY low delay after DS low MPDAT setup time before DS high Pulse width RDY low RDY high to DS high MPDAT hold time after DS high MPCS hold time after DS high MPADR hold time after DS high R/W setup time before DS low R/W hold time after DS high
Data Sheet
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ABM-3G PXF 4333 V1.1
Electrical Characteristics Table 8-7 No. 53 54 Microprocessor Interface Write Cycle Timing (Motorola) (cont'd) Limit Values Min MPCS low to RDY low impedance MPCS high to RDY high impedance 0 15 Typ Max ns ns Unit
Parameter
8.4.2.2
*
Microprocessor Read Cycle Timing (Motorola)
MPADR
60 68
MPCS
61 67
(MPRD) DS
71 72
(MPWR) R/W (MPRDY) RDY (DTACK) MPDAT
73
62
63
65
74
69
64
66
70
Figure 8-5 Table 8-8 No. 60 61 62 63 64 65
Microprocessor Interface Read Cycle Timing (Motorola) Microprocessor Interface Read Cycle Timing (Motorola) Limit Values Min Typ Max ns ns 20 5 SYSCLK
cycles
Parameter
Unit
MPADR setup time before MPCS low
MPCS setup time before DS low RDY low delay after DS low Pulse width RDY low MPDAT valid before RDY high RDY high to DS high
0 0 0 4 SYSCLK
cycles
ns
5 5
ns ns
Data Sheet
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ABM-3G PXF 4333 V1.1
Electrical Characteristics Table 8-8 No. 66 67 68 69 70 71 72 73 74 Microprocessor Interface Read Cycle Timing (Motorola) (cont'd) Limit Values Min MPDAT hold time after DS high MPCS hold time after DS high MPADR hold time after DS high DS low to MPDAT low impedance DS high to MPDAT high impedance R/W setup time before DS low R/W hold time after DS high MPCS low to RDY low impedance MPCS high to RDY high impedance 2 5 5 0 0 10 0 0 15 15 17 Typ Max ns ns ns ns ns ns ns ns ns Unit
Parameter
Data Sheet
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Electrical Characteristics
8.4.3
UTOPIA Interface
The AC characteristics of the UTOPIA Interface fulfill the standard of [3] and [4]. Setup and hold times of the 50 MHz UTOPIA Specification are valid. According to the UTOPIA Specification, the AC characteristics are based on the timing specification for the receiver side of a signal. The setup and the hold times are defined with regards to a positive clock edge, see Figure 8-6. Taking into account the actual clock frequency (up to the maximum frequency), the corresponding (min. and max.) transmit side "clock to output" propagation delay specifications can be derived. The timing references (tT5 to tT12) are according to the data found in Table 8-9 through Table 8-12. Note: The UTOPIA Receive Interface backplane-side is optimized for operation up to 60 MHz UTOPIA clock frequency to achieve a speed-up factor of 1.25 in bandwidth accepted from the backplane (respective values provided in brackets).
*
Clock
Signal
84, 86
85, 87
input setup to clock input hold from clock
Figure 8-6
Setup and Hold Time Definition (Single- and Multi-PHY)
Figure 8-7 shows the tristate timing for the multi-PHY application (multiple PHY devices, multiple output signals are multiplexed together).
*
Clock
88 89
Signal
90 91
signal going low impedance from clock
signal going low impedance to clock
signal going high signal going high impedance from clock impedance to clock
Figure 8-7
Data Sheet
Tristate Timing (Multi-PHY, Multiple Devices Only)
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Electrical Characteristics In the following tables, AP (column DIR, Direction) defines a signal from the ATM Layer (transmitter, driver) to the PHY Layer (receiver), AP defines a signal from the PHY Layer (transmitter, driver) to the ATM Layer (receiver). Both UTOPIA Interfaces (PHY-side and Backplane-side) can be configured in either Slave or Master Mode. If configured in Master Mode, the interface is considered to be the ATM Layer device (A) and if configured in Slave Mode, the interface is considered to be the PHY Layer device (P) respectively. All timings also apply to UTOPIA Level 1 8-bit data bus operation.
*
Table 8-9 No. 80 81 82 83 84 85
Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY) Description 0 40 4 1 Limit Values Min Max 52 60 5 2 MHz % % ns ns ns Unit
Signal Name DIR UTXCLKD, UTXCLKU
A>P TxClk frequency (nominal) TxClk duty cycle TxClk peak-to-peak jitter TxClk rise/fall time
UTXDATD, UTXDATU, UTXPRTYD, UTXPRTYU, UTXSOCD, UTXSOCU, UTXENBD, UTXENBU UTXCLAVD, UTXCLAVU
A>P Input setup to TxClk Input hold from TxClk
86 87
*
A

4 1
-
ns ns
Table 8-10 No. 80
Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY) Description Limit Values Min Max MHz 0 0 40 52 52 60 5 2 % % ns Unit
Signal Name DIR URXCLKD, URXCLKU
A>P RxClk frequency (nominal) URXCLKD: URXCLKU: RxClk duty cycle RxClk peak-to-peak jitter RxClk rise/fall time
81 82 83
Data Sheet
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Electrical Characteristics Table 8-10 No. 84 85 86 87 Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY) Description 4 1 4 1 Limit Values Min URXENBD, URXENBU URXDATD, URXDATU, URXPRTYD, URXPRTYU, URXSOCD, URXSOCU, URXCLAVD, URXCLAVU A>P Input setup to RxClk Input hold from RxClk A

Signal Name DIR
*
Table 8-11 No. 80 81 82 83 84 85
Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Multi-PHY) Description 0 40 4 1 Limit Values Min Max 52 60 5 2 MHz % % ns ns ns Unit
Signal Name DIR UTXCLKD, UTXCLKU
A>P TxClk frequency (nominal) TxClk duty cycle TxClk peak-to-peak jitter TxClk rise/fall time
UTXDATD, UTXDATU, UTXPRTYD, UTXPRTYU, UTXSOCD, UTXSOCU, UTXENBD, UTXENBU, UTXADRD, UTXADRU
A>P Input setup to TxClk Input hold from TxClk
Data Sheet
347
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Electrical Characteristics Table 8-11 No. 86 87 88 89 90 91 Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Multi-PHY) Description 4 1 Limit Values Min UTXCLAVD, UTXCLAVU A

Signal Name DIR
Signal going low impedance to 4 TxCLK Signal going high impedance to TxCLK Signal going low impedance from TxCLK Signal going high impedance from TxCLK 0 1 1
*
Table 8-12 No. 80
Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Multi-PHY) Description Limit Values Min Max MHz 0 0 40 4 1 52 52 60 5 2 % % ns ns ns Unit
Signal Name DIR URXCLKD, URXCLKU
A>P RxClk frequency (nominal) URXCLKD: URXCLKU: RxClk duty cycle RxClk peak-to-peak jitter RxClk rise/fall time
81 82 83 84 85 URXENBD, URXENBU, URXADRD, URXADRU
A>P Input setup to RxClk Input hold from RxClk
Data Sheet
348
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Electrical Characteristics Table 8-12 No. 86 87 88 89 90 91 Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Multi-PHY) Description 4 1 Limit Values Min URXDATD, URXDATU, URXPRTYD, URXPRTYU, URXSOCD, URXSOCU, URXCLAVD, URXCLAVU A

Signal Name DIR
Signal going low impedance to 4 RxCLK Signal going high impedance to RxCLK Signal going low impedance from RxCLK Signal going high impedance from RxCLK 0 1 1
Note: The setup and hold times for receive Interfaces deviate for non-standard 60 MHz operation. Timings are provided on request.
Data Sheet
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Electrical Characteristics
8.4.4
CPR SSRAM Interface
Timing of the Synchronous Static RAM Interfaces is simplified as all signals are referenced to the rising edge of RAMCLK. In Figure 8-8, it can be seen that all signals output by the ABM-3G have identical delay times with reference to the clock. When reading from the RAM, the ABM-3G samples the data within a window at the rising clock edge.
100
RAMCLK CPRADSC, CPRADR(18:0), CPRGW, CPROE CPRDAT(19:0), input
103
101
102
CPRDAT(19:0), output
104 105
Figure 8-8 Table 8-13 No. 100 100A 101
SSRAM Interface Generic Timing Diagram SSRAM Interface AC Timing Characteristics Limit Values Min Typ Max ns 52 2.5 MHz ns 19.2 Unit
Parameter
TRAMCLK: Period RAMCLK FRAMCLK: Frequency RAMCLK
Setup time CPRADSC, CPRADR(18:0), CPRGW, CPROE before RAMCLK rising
102 103 104 105
Hold time CPRADSC, CPRADR(18:0), 1.5 CPRGW, CPROE after RAMCLK rising Delay CPRDAT Output after RAMCLK 2.5 rising Setup time CPRDAT Input before CLK 2.5 rising (Read cycles) Hold time CPRDAT Input after CLK ris- 1.5 ing (Read cycles) 11
ns ns ns ns
Data Sheet
350
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Electrical Characteristics
8.4.5
CSR SDRAM Interface(s)
Timing of the Synchronous Dynamic RAM (SDRAM) Interface is simplified as all signals are referenced to the rising edge of RAMCLK. In Figure 8-9, it can be seen that all signals output by the ABM-3G have identical delay times with reference to the clock. When reading from RAM, the ABM-3G samples the data within a window at the rising clock edge.
110
RAMCLK CSRADRi(13:0), CSRRASi, CSRCASi, CSRCSi, CSRWEi, CSRBAi0, CSRBAi1 CSRDATi(31:0), input
113
111
112
CSRDATi(31:0), output
114 115
Figure 8-9 Table 8-14 No. 110 110A 111
Generic SDRAM Interface Timing Diagram SDRAM Interface AC Timing Characteristics Limit Values Min Typ Max ns 52 MHz ns 19.2 Unit
Parameter
TRAMCLK: Period RAMCLK FRAMCLK : Frequency RAMCLK
2.5 Setup time CSRADRi(13:0), CSRCSi, CSRRASi, CSRCASi, CSRWEi, CSRBAi0, CSRBAi1 before RAMCLK rising Hold time 1.5 CSRADRi(13:0), CSRCSi, CSRRASi, CSRCASi, CSRWEi, CSRBAi0, CSRBAi1 after RAMCLK rising Delay CSRDATi Output after RAMCLK rising 3 6.5
112
ns
113
ns
Data Sheet
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Electrical Characteristics Table 8-14 No. 114 115 SDRAM Interface AC Timing Characteristics (cont'd) Limit Values Min Setup time CSRDATi Input before RAMCLK rising 2.5 (Read cycles) Hold time CSRDATi Input after RAMCLK rising (Read cycles) 1.5 Typ Max ns ns Unit
Parameter
Data Sheet
352
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Electrical Characteristics
8.4.6
Reset Timing
power-on
VDD 151 CLK 150 RESET
Figure 8-10 Reset Timing Table 8-15 No. 150 151 Reset Timing Limit Values min. RESET pulse width 120 Number of SYSCLK cycles during 2 RESET active max. ns SYSCLK cycles Unit
Parameter
Note: RESET may be asynchronous to CLK when asserted or deasserted. RESET may be asserted during power-up or asserted after power-up. Nevertheless, deassertion must be at a clean, bounce-free edge.
Data Sheet
353
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Electrical Characteristics
8.4.7
Boundary-Scan Test Interface
160/ 160A 161 162
TCK
163 164
TMS
165 166
TDI
167/ 167A
TDO
168
TRST
Figure 8-11 Boundary-Scan Test Interface Timing Diagram Table 8-16 No. 160 160A 161 162 163 164 165 166 167 167A 168 Boundary-Scan Test Interface AC Timing Characteristics Limit Values Min Typ Max ns 10 40 40 10 10 10 10 30 30 200 MHz ns ns ns ns ns ns ns ns ns 100 Unit
Parameter
TTCK: Period TCK FTCK: Frequency TCK
TCK high time TCK low time Setup time TMS before TCK rising Hold time TMS after TCK rising Setup time TDI before TCK rising Hold time TDI after TCK rising Delay TCK falling to TDO valid Delay TCK falling to TDO high impedance Pulse width TRST low
Data Sheet
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Electrical Characteristics
8.5
Table 8-17 Parameter
Capacitances
Capacitances Symbol min. Limit Values max. 5 5 40 50 20 pF pF pF pF pF 2 2.5 Unit
Input Capacitance Output Capacitance Load Capacitance at: UTOPIA Outputs MPDAT(15:0), MPRDY other outputs
CIN COUT CFO1 CFO2 CFO3
8.6
Table 8-18 Parameter
Package Characteristics
Thermal Package Characteristics Symbol Ambient Temperature TA=25C TA=25C TA=25C RJA(0,25) RJA(0,25) RJA(0,25) 21,1 17,7 16,3 C/W C/W C/W Value Unit
Thermal Package Resistance Junction to Ambient Airflow No airflow Airflow 200 lfpm = 1 m/s Airflow 500 lfpm = 2.5 m/s
Data Sheet
355
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ABM-3G PXF 4333 V1.1
Test Mode
9
Test Mode
A Test Access Port (TAP) is implemented in the ABM-3G. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both the TAP controller and boundary scan meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 9-1 gives an overview about the TAP controller.
*
Test Access Port (TAP) TCK
CLOCK
Clock Generation CLOCK
1 2 Identification Scan (32 bit)
Pins
TRST
TMS
Test Control
TAP Controller
Control Bus
TDI
Data in
- Finite State Machine - Instruction Register (4 bit) - Test Signal Generator
Boundary Scan (n bit) n
Reset
. . .
ID Data out SS Data out
. . .
TDO
Enable Data out
Figure 9-1
Block Diagram of Test Access Port and Boundary Scan Unit
If no boundary scan operation is planned, TRST must be connected with VSS. TMS and TDI do not need to be connected since pull-up transistors ensure high input levels in this case. Nevertheless, it is good practice to set the unused inputs to defined levels. In this case, if the JTAG is not used: TMS = TCK = `1' is recommended. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input), and TDO (Test Data Output) when the TAP controller is not in its reset state; i.e., TRST is connected to VDD3 or it remains unconnected due to its internal pull up. Test data at TDI are loaded with a clock signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to another; constant `1' on TMS leads to normal operation of the chip. An Input pin (I) uses one boundary scan cell (data in); an Output pin (O) uses two cells (data out, enable); and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that most functional output and input pins of the ABM-3G are tested as I/O pins in boundary scan, thus using three cells. The boundary scan unit of the ABM-3G contains
Data Sheet
356
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ABM-3G PXF 4333 V1.1
Test Mode a total of n = 572 scan cells. The desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices on the board. In this test mode, at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (`0' or `1'). Then, the contents of the boundary scan are shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. INTEST supports internal testing of the chip; i.e., the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1'). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then, all input pins are updated for the following test cycle. SAMPLE/PRELOAD is a test mode which provides a snapshot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. Standard Mode The ID code field is set to: Version Part Number Manufacturer : 1H : 07F0H : 083H (including LSB, which is fixed to '1')
Alternate Mode The ID code field is set to Version Part Number Manufacturer : 1H : 07F0H : 083H (including LSB, which is fixed to '1')
Note: Since in test logic reset state the code `0011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state. BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle. CLAMP allows the state of signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. Signals driven from the ABM-3G will not change while the CLAMP instruction is selected. HIGHZ places all of the system outputs in an inactive drive state.
Data Sheet 357 2001-12-17
ABM-3G PXF 4333 V1.1
Package Outlines
10
*
Package Outlines
P-BGA-456 (Plastic Ball Grid Array Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 358
Dimensions in mm 2001-12-17
GPM05247
ABM-3G PXF 4333 V1.1
Glossary
11
AAL ABM ABM-3G ABR ALP AOP ATM BIST CAC CAME CBR CDV CLP CRC DSLAM dword EPD FIFO GFR I/O ITU-T LCI LIC LIFO LSB MBS MCR MSB OAM PCR
Data Sheet
Glossary
ATM Adaptation Layer ATM Buffer Manager device, PXB 4330E ATM Buffer Manager device, PXF 4333 Available Bit Rate ATM Layer Processor device, PXB 4350 E ATM OAM Processor device, PXB 4340 E Asynchronous Transfer Mode Built-In Self Test Connection Acceptance Control Content Addressable Memory Element device, PXB 4360 E Constant Bit Rate Cell Delay Variation Cell Loss Priority of standardized ATM cell Cyclic Redundancy Check Digital Subscriber Line Access Multiplexer double word (32 bits) Early Packet Discard First-In-First-Out buffer Guaranteed Frame Rate Input/Output International Telecommunications Union--Telecommunications standardization sector Local Connection Identifier Line Interface Card or Line Interface Circuit Last-In-First-Out buffer Least Significant Bit Maximum Burst Size Minimum Cell Rate Most Significant Bit Operation And Maintenance Peak Cell Rate
359 2001-12-17
ABM-3G PXF 4333 V1.1
Glossary PHY PPD PTI QID QoS RAM SCR SDRAM SID SSRAM TM UBR UTOPIA VBR-nrt VBR-rt VCVCC VCI VPVPC VPI WFQ word PHYsical Line Port Partial Packet Discard Payload Type Indication field of standardized ATM cell Queue IDentifier Quality of Service Random Access Memory Sustainable Cell Rate Synchronous Dynamic Random Access Memory Scheduler IDentifier Synchronous Static Random Access Memory Traffic Management Unspecified Bit Rate Universal Test and OPeration Interface for ATM Variable Bit Rate - non real time Variable Bit Rate - real time Virtual Channel specific Virtual Channel Connection Virtual Channel Identifier of standardized ATM cell Virtual Path specific Virtual Path Connection Virtual Path Identifier of standardized ATM cell Weighted Fair Queueing 16 bits
Data Sheet
360
2001-12-17
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Published by Infineon Technologies AG

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